The invention provides a method, a device and a system for operating a convolutional neural network on an FPGA (Field Programmable Gate Array), which are used for solving the problems of complicated implementation steps and high time cost when the convolutional neural network is operated on the FPGA in the prior art. The method comprises the steps that an upper computer calculates a compression scale for quantifying each calculation parameter of each convolutional layer of a convolutional neural network model according to a preset quantization bit width; According to the compression scale corresponding to each convolution layer, when the FPGA executes the operation of the convolutional layer, the FPGA is used for carrying out convolution calculation on the convolution layer to obtain a convolution kernel weight Wf, a shift scale parameter scale f1 for carrying out shift operation on a convolution calculation result of the convolution layer, and a bias Biasf for carrying out bias operation on a shift calculation result of the convolution layer; And the Wf, the scale f and the Biasf corresponding to each convolutional layer are written into the FPGA, so that when the FPGA operates the convolutional neural network model, the operation of the convolutional layer is executed based on the Wf, the scale f and the Biasf corresponding to each convolutional layer.

Method, device and system for operating convolutional neural network on FPGA

The invention provides a convolutional neural network accelerator based on an FPGA. The convolutional neural network accelerator comprises a controller, N paths of parallel operation processing units,a weight updating unit and a bias updating unit, the controller is connected with each path of operation processing unit; the weight updating unit and the bias updating unit are respectively connected with the controller and each path of operation processing unit; wherein the controller is based on the mth layer structure of the CNN; and reconstructing the connection relationship of the modules in each path of operation processing unit to match the mth layer structure, and respectively updating the weight and bias of the reconstructed operation processing unit by adopting the weight updatingunit and the bias updating unit to enable the reconstructed operation processing unit to process the information according to the processing mode of the mth layer structure. According to the accelerator provided by the embodiment of the invention, the operation of each layer in the CNN network is processed by means of the reconstruction of the operation unit, so that the reuse of resources is achieved, the realization of the CNN network on embedded equipment can be met, and the power consumption is reduced.

A convolutional neural network accelerator based on an FPGA

The invention provides a neural network representation standard framework, comprising: an interoperable representation module, which obtains an interoperable representation format by converting an input neural network, and comprises a syntax definition of the neural network, a supported operation definition and a weight format definition; a compact representation module, which converts the interoperable representation neural network into a serialized format by a neural network compression algorithm, which includes a syntax definition, a supported operation definition and a weight format definition of the compressed neural network; a coding and decoding representation module, which converts the compact representation of the neural network into a coding and decoding representation by a neural network compression algorithm, which comprises a syntax definition of the compressed neural network, a supported operation definition and a weight format definition after coding and decoding; and an encapsulation presentation module, which encapsulates the security information and the identity authentication information together with the neural network, thereby converting the neural network into a model.

Neural network representation standard framework

A method for accelerating Tensorflow system based on FPGA comprises the following steps of taking Python as upper client program library; encapsulating the module implemented by OpenCL as an interfacefor the upper client program to call; preparing FPGA operator development environment by OpenCL; developing FPGA operator by OpenCL; compiling internal accounting subsystem by OpenCL; integrating FPGA device into that entire system. The method of the invention reduces the development difficulty and ensures the stability and practicability of the FPGA as a device in the Tensorflow system.

Method for accelerating Tensorflow system based on FPGA

Disclosed herein are a neural network operating system and method. The system comprises: a software layer that is configured to, according to a preset network model and network model data corresponding to the preset network model, construct a neural network computational graph for a data stream computing architecture and allocate a computing space corresponding to the neural network computational graph; a driver layer that is connected to the software layer and is configured to carry out computing node initialization according to the computing space and use a data transmission channel between the driver layer and a hardware layer to transmit to the hardware layer node data of multiple computing nodes in the neural network computational graph; and the hardware layer, which is connected to the driver layer and is configured to use the data transmission channel to successively obtain the node data of the multiple computing nodes and perform computing according to the node data.

Neural network operating system and method

The invention discloses a method for accelerating an LSTM neural network algorithm on an FPGA platform. The FPGA is a field-programmable gate array platform and comprises a general processor, a field-programmable gate array body and a storage module. The method comprises the following steps that an LSTM neural network is constructed by using a Tensorflow pair, and parameters of the neural networkare trained; the parameters of the LSTM network are compressed by adopting a compression means, and the problem that storage resources of the FPGA are insufficient is solved; according to the prediction process of the compressed LSTM network, a calculation part suitable for running on the field-programmable gate array platform is determined; according to the determined calculation part, a softwareand hardware collaborative calculation mode is determined; according to the calculation logic resource and bandwidth condition of the FPGA, the number and type of IP core firmware are determined, andacceleration is carried out on the field-programmable gate array platform by utilizing a hardware operation unit. A hardware processing unit for acceleration of the LSTM neural network can be quicklydesigned according to hardware resources, and the processing unit has the advantages of being high in performance and low in power consumption compared with the general processor.

Design method of hardware accelerator based on LSTM recursive neural network algorithm on FPGA platform

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Design method of hardware accelerator based on LSTM recursive neural network algorithm on FPGA platform