The invention discloses an in-memory computing circuit suitable for a full-connection binary neural network which belongs to the technical field of basic electronic circuits. The circuit comprises aninput latch circuit, a counting addressing module, an address selector, a decoding and word line driving circuit, a storage array, a pre-charging circuit, a writing bit line driving circuit, a copyingbit line array unit, a sequential control circuit, a sensitive amplifier, an NAND gate array, an output latch circuit and an analog delay chain. Parallel XNOR operation is executed on an SRAM bit line, and accumulation, activation and other operations are executed by a delay chain in a time domain. Because partial calculation is completed while data is read, and the delay chain with small area occupation can be integrated with the SRAM, the energy consumption of the memory access process is reduced, the throughput of the system is also improved by multi-column parallel calculation, and compared with an accelerator adopting a Von Noemann architecture, the overall power consumption of the network can be remarkably reduced, and the energy efficiency is improved.

In-memory computing circuit suitable for full-connection binary neural network

The invention relates to an activation function calculation unit for quantized LSTM, and the activation function calculation unit is characterized in that the activation function calculation unit comprises a sigmoid function calculation unit and a tanh function calculation unit; the tanh function calculation unit comprises a first complement code solving unit, a second complement code solving unit, an amplitude comparator, an arithmetic operation unit, a first selector and a second selector. According to the activation function calculation unit for the quantized LSTM provided by the invention,after the operand for the LSTM network is quantized, the operand bit width of the activation function calculation unit is determined according to the network precision, the noise margin and the bit width requirement of the offset coefficient in the linear function for the operand. For the operands with the bit width of 8 bits, a linear function expression used for approximating an activation function is determined. A corresponding calculation unit is designed for the linear function expression. A booth algorithm is used, and simple shift addition is used to quickly calculate the multiplication with a fixed coefficient.

Activation function calculation unit for quantized LSTM

The invention discloses a configurable neural network activation function implementation device. The device comprises a controller, a symbol judgment module, a range detection module, a parameter register, a floating point multiplier, a floating point adder, a phase operand arithmetic unit, an address generator, a lookup table, a first gating latch and a second gating latch. The operation of a sigmoid function and a panh function is achieved by configuring a control signal M. The device is simple in achieving structure, the synchronous clock design is adopted, the time sequence checking and the verification are convenient, the area is small, the power consumption is low, the implementation on a chip is convenient, and the practicability of the embedded application is enhanced. When the device is used for calculating the neural network activation function, the processing flow is simple and easy to control, and the calculation efficiency of the neural network activation function is improved. The device can conveniently expand the address generator module and the lookup table module to meet the requirement of function precision conversion according to the requirement of tanh calculation precision. Therefore, the method is an ideal structure for realizing the embedded neural network processor activation function.

A configurable neural network activation function implementation device

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A configurable neural network activation function implementation device