Basic flip-flop structures are compared with the main emphasis on CMOS ASIC implementations. Flip-flop properties are analyzed by means of simplified models, some structural approaches for optimized metastable behavior are discussed. A special integrated test circuit which facilitates accurate and reproducible measurements is presented. The circuit has been used for carrying out metastability measurements in a wide temperature and voltage range to predict circuit parameters for worst-case designs. Results from measurements and circuit simulation indicate that different criteria for optimizing flip-flop performance should be used for synchronizers and for those applications where the observation of timing constraints imposed on flip-flop input signals can be guaranteed. These results can help in determining the reliability of existing synchronizer and arbiter designs. By means of special synchronizer cells the reliability of asynchronous interfaces can be improved significantly, enabling the system design to gain speed and flexibility in communication between independently clocked submodules. >

Metastability behavior of CMOS ASIC flip-flops in theory and test

An apparatus for self-timed algorithmic execution comprises a functional logic set, a reference clock input and a pulse sequencer. The functional logic set receives input data in synchrony with a reference pulse set received at the reference clock input; performs algorithmic computations on the input data at a maximal-rate set by the pulse sequencer in accordance with the physical characteristics of the functional logic; generates output data; and transmits the output data in synchrony with the reference pulse set. The maximal-rate set by the pulse sequencer is independent of the reference pulse set. A method for self-timed algorithmic execution comprises the steps of: transferring input data to a functional logic set in synchrony with a reference clock; generating a maximal-rate pulse sequence, for driving the functional logic set at a rate dependent upon an algorithm execution time for the functional logic set but independent of the reference clock; generating output data from the functional logic set in response to the maximal-rate pulse sequence; and transferring the output data from the functional logic in synchrony with the reference clock.

Apparatus and method for self-timed algorithmic execution

An approach is presented to high-performance asynchronous architectures offering significant advantages over conventional clocked systems, without some of the drawbacks normally associated with asynchronous techniques. As the level of integration increases, an asynchronous wavefront array designed using the techniques described will have three important advantages over the equivalent synchronous systolic array: faster throughput (rate at which data are clocked through a system), reduced design complexity, and greater reliability. The benefits and drawbacks of using the asynchronous technique are highlighted using three wavefront arrays: two one-dimensional multipliers, and a two-dimensional sorter. All three can be built using just one basic building block. >

Four state asynchronous architectures

This paper develops a temporal process algebra, CSA, for reasoning about distributed systems that involve qualitative timing constraints. It is a conservative extension of Milner's CCS that combines the idea of multiple clocks from the algebra PMC with the assumption of maximal progress familiar from timed process algebras such as TPL. Using a typical class of examples drawn from hardware design, we motivate why these features are useful and in some cases necessary for modeling and verifying distributed systems. We also present fully-abstract behavioral congruences based on the notion of strong bisimulation and observational equivalence, respectively. For temporal strong bisimulation we give sound and complete axiomatizations for several classes of processes.

An Algebraic Theory of Multiple Clocks

In this paper we introduce a novel approach to the specification of real-time behaviour with process algebras. In contrast to the usual pattern, involving a fixed, measurable, and global notion of time, we suggest to represent real-time constraints indirectly through uninterpreted clocks enforcing broadcast synchronization between processes. Our approach advocates the use of asynchronous process algebras, which admit the faithful representation of nondeterministic and distributed computations.

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An asynchronous process algebra with multiple clocks

Numerous papers have discussed the behavior of flip-flops in synchrronization and arbitration circuits. Here, a nonconventional machine, which avoids completely synchronization failures by using metastability detectors in conjunction with a stretchable clock, is evaluated. The core of the paper focuses on the quantitative evaluation of the performance and reliability of this unconventional kind of machine. Only synchronization and arbitration failures are considered here, so when these machines are compared to conventional ones, all other factors affecting reliability and performance (e.g., technology, fabrication, etc.) are kept invariant. The MTBF's and a new normalized throughput measure show they can run substantially faster and more reliably than functionally equivalent, conventional machines with fixed clocks. Integrrated circuit implementations have been built and successfully tested.

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Reliable High-Speed Arbitration and Synchronization