Modeling Sigma-delta Modulator Non-Idealities in SIMULINK

This paper presents a compact and power efficient third-order continuous-time (CT) delta-sigma ( $\Delta \Sigma $ ) analog-to-digital converter (ADC) with a single operational transconductance amplifier (OTA). A 4-bit second-order fully passive noise-shaping (NS) successive-approximation-register (SAR) ADC is employed as the quantizer while inherently provides two additional NS orders. Fabricated in 40-nm CMOS, the prototype occupies 0.029 mm2 of active area and consumes 1.16 mW of power when clocked at 500-MHz sampling frequency. The proposed CT $\Delta \Sigma $ ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.4 dB over 12.5-MHz bandwidth, yielding a Walden figure of merit (FoM) of 17 fJ/conversion-step.

A 0.029-mm 2 17-fJ/Conversion-Step Third-Order CT $\Delta\Sigma$ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer

The emerging noise-shaping (NS) successive approximation (SAR) architecture is highly efficient and compact; however, the order and signal-to-noise ratio (SNR) of sub-MHz NS SAR ADCs are still lower than conventional sigma–delta ADCs. This work proposes a cascaded NS (CaNS) SAR architecture that increases system order and enables more effective NS for higher SNR. The proposed architecture enhances the robustness of high-order NS performance at the system level and is inherently process, voltage and temperature (PVT) stable. A two-phase settling technique improves the efficiency of residue amplification without sacrificing robustness. A prototype CaNS SAR ADC, fabricated in 28-nm CMOS, occupies 0.02 mm2 and consumes 120 $\mu \text{W}$ . The measured Signal to Noise and Distortion Ratio (SNDR) over 100-kHz bandwidth is 88 dB, resulting in a Schreier Figure of Merit (FoM) of 177 dB.

A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension

In this paper, we proposed an improved mobile fronthaul architecture employing the SNR-improved delta-sigma digitization scheme and 4-level pulse amplitude modulation (PAM-4) format. Different from traditional 2-bit quantization, this scheme deploys two-fold delta-sigma quantization, which uses 1-bit delta-sigma modulator to quantize the signal, and another 1-bit delta-sigma modulator to quantize the in-band noise. A significant reduction of the in-band noise can be achieved only applying a differentiator, bringing about a much better noise shaping performance. Meanwhile, the two 1-bit streams can be combined and transmitted in a PAM-4 manner through an intensity modulation direct detection (IM-DD) channel. We have successfully experimentally demonstrated the digitization and transmission of 65536 quadrature amplitude modulation (QAM) baseband orthogonal frequency division multiplexing (OFDM) signal with sampling rate of 1.25 GSa/s over 20-km fiber with standard 10-Gbaud PAM-4 signal, with a signal to noise ratio (SNR) of 57.7 dB. Compared to the conventional 2-bit quantized OFDM scheme, experimental results show that a significant SNR improvement of 17.7 dB has been achieved by the proposed scheme. In addition, we also realized a transmission of 16384-QAM intermediate frequency (IF) signal at the center frequency of 3.5 GHz (with an SNR of 49.6 dB). An improvement of 15.9 dB can also be maintained.

An SNR-improved Transmitter of Delta-sigma Modulation Supported Ultra-High-Order QAM Signal for Fronthaul/WiFi Applications

This paper introduces a voltage-controlled oscillator (VCO)-based nonuniform sampling (NUS) analog-to-digital converter (ADC), which shifts the conventional voltage-domain level crossing to the phase domain, thus eliminating the need for any continuous-time (CT) comparator or reference generator. It increases the signal bandwidth and reduces the implementation costs of both analog and digital circuitries compared to the existing voltage-domain NUS ADCs. The signal-to-quantization-noise ratio (SQNR) is improved by the first-order noise shaping and inherent dithering via the free-running oscillation of VCO. The quantization error of the proposed architecture is analyzed, and a phase-domain calibration on the VCO nonlinearity is proposed. Due to the mostly digital architecture and time-based nature of the proposed architecture, the performance and figure of merit (FOM) are expected to improve with the scaled technology. This prototype achieves 200-MHz bandwidth with 60-dB dynamic range (DR) and consumes 19.7 mW of power with an active area of 0.13 mm2 in 65-nm complementary metal–oxide–semiconductor (CMOS), where the nonuniform digital signal processing (DSP) is performed off chip. The estimated power and area of the nonuniform DSP including the calibration and decimation filter are 30 mW and 0.114 mm2, respectively.

A Noise-Shaped VCO-Based Nonuniform Sampling ADC With Phase-Domain Level Crossing

This paper presents a new second-order temperature-compensated current reference which uses only one resistor. The behavior of the proposed bias circuit is analyzed in this paper, and the current reference circuits were designed and simulated in a 130 nm CMOS technology. From the simulation results, the proposed current reference achieved 327 ppm/°C in the temperature range of −30 °C to +150 °C, which is very wide. Its nominal current is 27 nA with a current variation of + 3% at a supply voltage of 1.2 V. Compared to a conventional first-order temperature-compensated current bias circuit designed for nano-amperes, the proposed current reference provides a current that is 4.7 times more stable over the temperature range of −30 °C to +150 °C. Also, the current drift from process corner variations deviates less than 3.7% from the simulation results.

A nano-ampere 2nd order temperature-compensated CMOS current reference using only single resistor for wide-temperature range applications

Certain aspects of the present disclosure provide a delta-sigma modulator (DSM) using time-interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs). For example, two SAR ADCs may be configured to alternately sample and process an input signal and provide a feedback signal for the DSM using excess loop delay (ELD). In other aspects, the DSM may be implemented using a two-step SAR quantizer. For example, a first SAR ADC may sample an input signal to generate a most-significant bit (MSB) portion of an output of the DSM, while the second SAR ADC may subsequently sample a residue from the first SAR ADC conversion and generate a least-significant bit (LSB) portion of the output of the DSM. With these techniques, higher bandwidths may be obtained in high accuracy delta-sigma ADCs without using increased sampling rates.

Delta-sigma analog-to-digital converter (ADC) with time-interleaved (TI) or two-step successive approximation register (SAR) quantizer

This paper presents an efficient noise coupling scheme in time-interleaved delta-sigma modulators (DSMs). The traditional voltage domain quantization error extraction is replaced with time domain method which is inherently available in the noise-shaped integrating quantizers (NSIQs). Thus, no digital-to-analog converter is required for the noise-coupling. A modified NSIQ scheme is proposed, which not only allows the use of the NSIQ with an even number of time-interleaving, but also increases the overall noise transfer function (NTF) order. Along with an additional order of NTF in the NSIQ, a higher order NTF can be achieved by interleaving and noise-coupling multiple channel NSIQs and DSMs. The proposed time-interleaved noise-coupling NSIQ can be used as a stand alone analog-to-digital converter, or as a quantizer in time-interleaved DSMs. Mathematical analysis and MATLAB simulation results are provided to prove the efficiency of the proposed scheme.

Time-Interleaved Noise-Coupling Delta-Sigma Modulator Using Modified Noise-Shaped Integrating Quantizer

This paper describes a delta-sigma modulator with a new feedback topology in combination with the recently proposed two-step residue-discharging quantizer. Instead of using a single digital-to-analog converter (DAC) with a large number of levels, a mixed-mode DAC is presented which takes advantage of the two-step nature of the quantizer. Hence, only one feedback DAC, which is associated with the coarse bits (MSBs), is required for the modulator and LSBs are fed back as a time-modulated pulse (TMP). Therefore, high quantization resolution is achieved without increasing the front-end DAC complexity. Additionally, a new data weighted averaging (DWA) technique is proposed which not only suppresses the mismatch between the unit elements of the MSB DAC, but also aims to average out the gain error between the MSB and LSB DACs. Therefore, the possible quantization noise leakage is drastically reduced. Detailed mathematical models as well as comprehensive simulation results are provided to prove the efficiency of the proposed structure.

Noise-Shaped Residue-Discharging Delta-Sigma ADCs With Time-Modulated Pulse Feedback

This paper combines the benefits of the Sturdy-MASH delta-sigma modulator with the benefits of the noise-shaped integrating quantizer. By using the noise-shaped integrating quantizer, the first stage quantization error is directly extracted in time-domain without the need for any extra hardware. This removes the loading on the first loop filter, and allows accurate inter-stage gain scaling. The second loop output is also provided in a time-modulated pulse which operates a DAC at the front-end of the modulator. With the use of dual-DAC data weighted averaging, the mismatch between the front-end DACs is greatly suppressed. Detailed Matlab simulation results are provided to prove the efficiency of the proposed structure.

Sturdy-MASH delta-sigma modulator with noise-shaped integrating quantizer and dual-DAC DWA

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

Changsok Han

Author Tools

Chat about Author