This paper presents a chip-level post-complementary metal oxide semiconductor (CMOS) processing technique for 3-D integration and through-silicon-via (TSV) fabrication. The proposed technique is based on dry-film lithography, which is a low-cost and simple alternative to spin-coated resist. Unlike conventional photolithography methods, the technique allows resist patterning on very high topography, and therefore chip-level photolithography can be done without using any wafer reconstitution approach. Moreover, this paper proposes a via sidewall passivation method which eliminates dielectric etching at the bottom of the via and simplifies the whole integration process. In this paper, two 50- μm-thick chips were post-processed, aligned, bonded, and connected by Cu TSVs, which have parylene sidewall passivation. Daisy-chain resistance measurements show 0.5- Ω resistance on average for 60- μm-diameter TSVs, with a yield of more than 99% for 1280 TSVs from five different chip stacks. Subsequently, the techniques were applied to CMOS microprocessor stacking as a test vehicle. Die-level post-CMOS processing for 40- μm-diameter via etching, redistribution layer patterning, and chip-to-chip bonding were successfully demonstrated with the real chips.

/pdf/post-cmos-processing-and-3-d-integration-based-on-dry-film-46hpk6ca3b.pdf

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

Nanoimprint lithography is a high-resolution, high-throughput and low-cost technology to pattern nanostructure, but it only works well on planar surface. To solve this issue, a hybrid nanoimprint-soft Lithography (HNSL) was developed to pattern nanostructures on highly curved surfaces (e.g. the sidewall of an optical fiber). Moreover, double transfer UV-curing nanoimprint lithography, an improved version of HNSL, was introduced to enable high fidelity pattern transfer. Optical fibers can be patterned using this technology, and that opened the door to numerous applications.

Hybrid Nanoimprint-Soft Lithography for Highly Curved Surface with Sub-15 nm Resolution

Spin-on is the method of choice for the deposition of thin film polymers and photo-resists for standard WLP-processes like wafer bumping and redistribution. Topography and deep via holes are the challenges for the 3-D packaging technologies. For examples the depth and the diameter of TSV (through silicon via) and Si-trenches can be in a range of multiple 10-μms being far away for spin-on processes which are needed for lithography of wiring systems and side wall passivation processes. A comparison of different coating techniques has been compared in this paper: For spray-coating the polymer precursors have to be modified by dilution with appropriate solvents. Guidance for the selection of solvents for different material combinations will be discussed. A new technology called diffusion coating by the authors has been introduced in this paper. The process is based on a modified spin-on technique. Highly conformal coatings can be achieved for a wide range of materials. Patents are pending. Electrophoretic coating is a special deposition process using electroplating. Dry-film photo-resist by lamination is the process of choice if only the surface of the wafer has to be structured. The main advantage is that no liquid-based resists may flow into TSV or other cavities.

Coating techniques for 3D-packaging applications

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Coating techniques for 3D-packaging applications