In the past decades, photocatalytic CO2 reduction has remained a prominent and growing research field due to the efficient conversion of CO2 to value-added chemicals. Among various photocatalytic performance, the...

Highly Selective Semiconductor Photocatalysis for CO2 reduction

The display device has a significant contribution to the total power, which is critical for mobile consumer-electronic devices due to a limited battery capacity. We develop a power model of the active-matrix organic light-emitting diode (AMOLED) display and analyze the power contribution of thin-film transistor (TFT), OLED, and ${V_{\rm DD}}$ line drop. Both theoretical analysis and calculation are derived from TFT mobility, OLED luminous efficiency, pixel aperture ratio, and ${V_{\rm DD}}$ line drop. The TFT mobility from ${0.1}$ to ${10}\; \text{cm}^{2}/(\text{V}\cdot \text{s})$ is a bottleneck of display power. Metal oxide TFT may be more suitable for AMOLED display since relatively high mobility and low fabrication temperature. High luminous efficiency of OLED and top emission structure can decrease power consumption abundantly. The impact of copper wire technology is also discussed in large-size panels.

Power Consumption Model for AMOLED Display Panel Based on 2T-1C Pixel Circuit

Amorphous IGZO thin-film transistors (TFTs) in an etch stop layer (ESL) structure was processed on 2500 mm $\times $ 2200 mm size substrate. The fabricated devices exhibit enhancement mode characteristics, and excellent uniformity over large area. The presented good operational stabilities under both positive gate bias temperature stress (PBTS) and negative gate bias temperature stress (NBTS) tests can well meet the requirements for pixel switching. However, considering even threshold voltage shift under long term positive bias stress might affect proper operation of the gate driver on array (GOA), a design with a pulse gating scheme is proposed, consisting of 13 TFTs and 1 capacitor, to avoid long term continuous bias stressing of the TFT. With the proposed GOA design, a 32-inch QUHD ( $7680\times 4320$ ) high-resolution liquid crystal display (LCD) panel with a 7 mm wide bezel is achieved. The reliability of the GOA circuit is well proved through standard aging tests.

/pdf/robust-gate-driver-on-array-based-on-amorphous-igzo-thin-1ekanficxp.pdf

Robust Gate Driver on Array Based on Amorphous IGZO Thin-Film Transistor for Large Size High-Resolution Liquid Crystal Displays

The gate bias stress-induced threshold voltage shift effect of amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) with Cu gate is investigated in this brief. It is revealed that the Cu-gated TFTs with SiOx gate insulator suffer from serious electrical performance degradation under gate bias stress owing to Cu diffusion into the gate insulator and channel region. A stacked gate insulator of SiOx/SiNx is then proposed to suppress the Cu diffusion. Experimental results show that the Cu-gated TFTs with the stacked gate insulators have a comparable threshold voltage shift effect with that of the conventional TFTs with Mo electrode and SiOx insulator, under both positive and negative gate bias stresses.

Gate Bias Stress-Induced Threshold Voltage Shift Effect of a-IGZO TFTs with Cu Gate

Amorphous indium—gallium—zinc oxide (a-IGZO) materials have been widely explored for various thin-film transistor (TFT) applications; however, their device performance is still restricted by the intrinsic material issues especially due to their non-crystalline nature. In this study, highly crystalline superlattice-structured IGZO nanowires (NWs) with different Ga concentration are successfully fabricated by enhanced ambient-pressure chemical vapor deposition (CVD). The unique superlattice structure together with the optimal Ga concentration (i.e., 31 at.%) are found to effectively modulate the carrier concentration as well as efficiently suppress the oxygen vacancy formation for the superior NW device performance. In specific, the In1.8Ga1.8Zn24O7 NW field-effect transistor exhibit impressive device characteristics with the average electron mobility of ~ 110 cm2·V−1·s−1 and on/off current ratio of ~ 106. Importantly, these NWs can also be integrated into NW parallel arrays for the construction of high-performance TFT devices, in which their performance is comparable to many state-of-the-art IGZO TFTs. All these results can evidently indicate the promising potential of these crystalline superlattice-structured IGZO NWs for the practical utilization in next-generation metal-oxide TFT device technologies.

Crystalline InGaZnO quaternary nanowires with superlattice structure for high-performance thin-film transistors

High‐performance bilayer In2O3/IGZO thin‐film transistors (TFTs) fabricated by pulsed laser deposition are reported. The TFTs exhibit an on/off current ratio of 109, a reversed subthreshold slope (ss) of 0.08 V dec−1, and a high saturation mobility of 47.9 cm2 V−1 s−1. The reliability of the mobility values is critically validated and assessed by four‐probe measurements, the transfer‐length method, and the temperature‐dependence. X‐ray photoelectron spectra are combined with C–V measurements to characterize the interface, and the results show that a two‐dimensional electron gas (2DEG)‐like state accumulates at the In2O3/IGZO interface. However, this state only forms in the subthreshold region and does not cause the high carrier mobility in the region above the threshold. Instead, the enhanced carrier mobility results from the intrinsic high mobility of the In2O3, the smooth surface, and the low‐defect states in the In2O3/IGZO bilayer with a good percolation transport path.

Critical Assessment of the High Carrier Mobility of Bilayer In2O3/IGZO Transistors and the Underlying Mechanisms

Amorphous oxide semiconductor thin‐film transistors (AOS TFTs) are ever‐increasingly utilized in displays. However, to bring high mobility and excellent stability together is a daunting challenge. Here, the carrier transport/relaxation bilayer stacked AOS TFTs are investigated to solve the mobility‐stability conflict. The charge transport layer (CTL) is made of amorphous In‐rich InSnZnO, which favors big average effective coordination number for all cations and more edge‐shared structures for better charge transport. Praseodymium‐doped InSnZnO is used as the charge relaxation layer (CRL), which substantially shortens the photoelectron lifetime as revealed by femtosecond transient absorption spectroscopy. The CTL and CRL with the thickness suitable for industrial production respectively afford minute potential barrier fluctuation for charge transport and fast relaxation for photo‐generated carriers, resulting in transistors with an ultrahigh mobility (75.5 cm2 V−1 s−1) and small negative‐bias‐illumination‐stress/positive‐bias‐temperature‐stress voltage shifts (−1.64/0.76 V). The design concept provides a promising route to address the mobility‐stability conflict for high‐end displays.

https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/advs.202300373

Addressing the Conflict between Mobility and Stability in Oxide Thin‐film Transistors

The Improved Properties of Solution-Based Ingasno (Igto) Thin Film Transistor Using the Modification of Inzno (Izo) Layer

We have developed 10-inch 300PPI and 65-inch ultra high-definition FFS LCD using amorphous In-Ga-Zn-O(IGZO) TFT. After improvement of TFT's process and structure, the TFT performance is good enough for TFT-LCD. In this report, we discuss our IGZO TFT process, uniformity and reliability.

10.4: Improvement of Stability on a‐IGZO LCD

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