The invention discloses a Cache data processing method and a Cache. The cache data processing method comprises the steps that a Cache receives address information, sent by a CPU, of a Main memory, andthe address of the Main memory comprises a Main memory Tag field and a Cache set index field; the Cache searches a Loop table according to the Main memory Tag field so as to obtain a mapping offset value; the Cache adds the mapping offset value and the value of the Cache set index field so as to obtain a line address of the Cache; the Cache reads the Cache memory Tag stored in the line address, aand compares the Main memory Tag field with the Cache memory Tag, and if the Main memory Tag field is consistent with the Cache memory Tag, outputting the data stored in the line address to the CPU by the Cache. According to the Cache data processing method and the Cache, the side channel attack based on the Cache access time can be effectively avoided, the hardware implementation is simple, andthe CPU operation efficiency is not greatly influenced.

Cache data processing method and Cache

A Gaussian sampling circuit resistant to simple power consumption analysis attacks. The Gaussian sampling circuit comprises: a control module, a random number generation module, a binary comparison module, a first single-port RAM, a sampling result output module and a power consumption information concealing module, wherein the control module is used for controlling the state transition and enabling of the circuit; the random number generation module generates uniformly distributed random numbers by means of a shift register; the binary comparison module locates, by means of a binary search algorithm, addresses of the random numbers in a distribution cumulative function table with a Gaussian distribution; the sampling result output module performs a modulus operation on the located addresses to form sampling outputs; and the power consumption information concealing module generates a random power consumption by means of searching, in a binary manner, for the addresses of the random numbers in a pseudo-distribution cumulative function table. According to the Gaussian sampling circuit composed of same, power consumption information during a sampling process can be effectively concealed, and the characteristic of resistance to selective-input simple attack analysis is realized.

Gaussian sampling circuit resistant to simple power consumption analysis attacks

The invention provides a lookup table operator for a reconfigurable processing system. The lookup table operator is characterized by comprising multiple lookup table units S-Box, and each lookup tableunit S-Box includes at least one lookup table, wherein input data is input to the lookup table operator, and one or more lookup table units S-Box in the lookup table operator process the input data.The invention further provides a lookup table operator collocation method used for the reconfigurable processing system.

Lookup table operator for reconfigurable processing system and collocation method thereof

The invention discloses a safety reconfigurable framework capable of resisting power dissipation attack, which comprises a multi-line reconfigurable array operation line, a line controller, a general register file, a register, an input cache, an output cache, a reconfigurable search table, a first multichannel data selector, a secret share safety protection module and a data path dynamic reconfiguration safety protection module, wherein the reconfigurable search table comprises an arithmetical logic unit, a data replacing network, a data loading unit and a data output unit; the secret share safety protection module comprises a second multichannel data selector, an XOR operation module, a data cache module and a first random number generator; the data path dynamic reconfiguration safety protection module comprises a third multichannel data selector, a fourth multichannel data selector, a second random number generator, a third random number generator, a first delay data channel and a second delay data channel. The safety reconfigurable framework has advantages of guaranteeing safety while greatly reducing area and performance cost.

Safety reconfigurable framework capable of resisting power dissipation attack

The invention discloses a block cipher algorithm-oriented reconfigurable S box. A gate control switch circuit is added to the S box and used for controlling an enable signal of the S box to be in a valid or invalid state so as to control whether the S box is subjected to table lookup operation or not. The invention furthermore discloses a reconfigurable computing array adopting the reconfigurable S box. The reconfigurable computing array comprises multiple computing resource blocks; each computing resource block comprises a group of S box resources and multiple groups of arithmetical logic resources; and the multiple groups of the arithmetical logic resources share the group of the S box resources. In addition, the invention discloses a gate control method for the reconfigurable S box. Multiple block cipher algorithms can be realized; the performance is high; the flexibility is high; the circuit realization area is small; the power consumption is low; and the S box can be subjected to fine-grained control.

Block cipher algorithm-oriented reconfigurable S box, reconfigurable computing array and gate control method

The invention provides a reconfigurable system configuration controller comprising: a configuration storage module which comprises a configuration packet storage device and a configuration group storage device, wherein the configuration packet storage device is used for storing configuration packets and the configuration group storage device is used for storing configuration groups; a configuration packet analysis module used for analyzing the configuration packets, generating configuration group indexes and configuration group effective flag bits and outputting the same to a configuration group reading module; the configuration group reading module used for reading effective configuration groups from the configuration group storage device according to the configuration group indexes and the configuration group effective flag bits; a configuration group reconfiguration module used for starting or stopping a reconfiguration process and a pipeline execution process of calculating arrays according to whether the configuration groups are in position or not and whether input data are in position or net. The reconfigurable system configuration controller can reduce power consumption of reconfigurable systems and improve the calculating performance of reconfigurable systems.

A reconfigurable system configuration controller and a pipeline scheduling method thereof

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Papers

Safety reconfigurable framework capable of resisting power dissipation attack

Block cipher algorithm-oriented reconfigurable S box, reconfigurable computing array and gate control method

A reconfigurable system configuration controller and a pipeline scheduling method thereof