In the context of hardware systems, authentication refers to the process of confirming the identity and authenticity of chip, board and system components such as RFID tags, smart cards and remote sensors. The ability of physical unclonable functions (PUF) to provide bitstrings unique to each component can be leveraged as an authentication mechanism to detect tamper, impersonation and substitution of such components. However, authentication requires a strong PUF, i.e., one capable of producing a large, unique set of bits per device, and, unlike secret key generation for encryption, has additional challenges that relate to machine learning attacks, protocol attacks and constraints on device resources. In this paper, we describe the requirements for PUF-based authentication, and present a PUF primitive and protocol designed for authentication in resource constrained devices. Our experimental results are derived from a 28 nm Xilinx FPGA.1

PUF-Based Authentication

Physically Unclonable Functions (PUFs) provide a unique signature for integrated circuits (ICs), similar to a fingerprint for humans. They are primarily used to generate secret keys, hereby exploiting the unique manufacturing variations of an IC. Unfortunately, PUF output bits are not perfectly reproducible and non-uniformly distributed. To obtain a high-quality key, one needs to implement additional post-processing logic on the same IC. Fuzzy extractors are the well-established standard solution. Pattern Matching Key Generators (PMKGs) have been proposed as an alternative. In this work, we demonstrate the latter construction to be vulnerable against manipulation of its public helper data. Full key recovery is possible, although depending on system design choices. We demonstrate our attacks using a 4-XOR arbiter PUF, manufactured in 65nm CMOS technology. We also propose a simple but effective countermeasure.

https://lirias.kuleuven.be/bitstream/123456789/450109/2/article-2419.pdf

Attacking PUF-Based Pattern Matching Key Generators via Helper Data Manipulation

In this paper, we show that a software implementation of CCA secure Saber KEM protected by first-order masking and shuffling can be broken by deep learning-based power analysis. Using an ensemble of deep neural networks created at the profiling stage, we can recover the session key and the long-term secret key from 257xN and 24x257xN traces, respectively, where N is the number of repetitions of the same measurement. The value of N depends on the implementation, environmental factors, acquisition noise, etc.; in our experiments N=10 is enough to succeed. The neural networks are trained on a combination of 80% of traces from the profiling device with a known shuffling order and 20% of traces from the device under attack captured for all-0 and all-1 messages. "Spicing" the training set with traces from the device under attack helps minimize the negative effect of device variability.

Breaking Masked and Shuffled CCA Secure Saber KEM by Power Analysis

Wireless sensor networks are widely deployed and implicitly characterized by stringent energy and computation constraints. Sensor nodes are vulnerable to false positive and false negative attacks that inject false data through compromised nodes. Such attacks cause false alarms with energy drain and information loss. Although several en-route filtering schemes have been designed to detect the attacks, they focus on saving energy through early filtering or continuous delivery of data in accordance with verification records; they cannot exclude compromised nodes. In this paper, we propose a scheme that effectively identifies the compromised nodes and copes with new attacks using a context-aware architecture. In addition, the proposed scheme improves the security strength and energy efficiency of the network. Simulation results validate that the proposed scheme provides energy savings of up to 45 percent and allows fewer attack successes than the existing scheme.

Context-Aware Architecture for Probabilistic Voting-based Filtering Scheme in Sensor Networks

A reliable PUF in a dual function SRAM

The widespread embedding of electronic devices into the daily-life objects, and their integration in the so called Internet of the Things (IoT), has raised a number of challenges for the design of Systems-on-Chip (SoCs) devices. Tiny manufacturing costs, stringent security, and ultra-low power operation constraints have considerably raised SoC design requirements. More than incremental approaches which try to re-use current cryptographic mechanisms, the new generation of IoT devices will require novel solutions which deeply integrate their hardware-intrinsic features to program execution. This paper proposes a low-cost PUF-based authentication architecture aiming to secure code execution in IoT SoCs. The solution is deeply embedded into the processor micro-architecture, so as to minimize re-design costs and performance penalties. This new architecture model not only deals with the most common threats against code and data authenticity and integrity, but also provides an approach to extract from processor's caches a stable and unpredictable key that is used in the code and data authentication process.

Computer security by hardware-intrinsic authentication

A fundamental property of Physical Unclonable Functions (PUFs) is uniqueness, which results from the intrinsic characteristics of each PUF instance. However, PUF architectures employ elements whose physical characteristics and behavior may be very similar among different instances, thus leaking unwanted information. We explore the consequences of this effect by mounting Template Attacks over XOR Arbiter PUFs. In the attack, Challenge-Respose Pairs (CRPs) are profiled in one FPGA instance of the PUF to predict responses of a different FPGA instance, obtaining up to 80% of accuracy. We show that replicating the same attack strategy with a well-known Machine Learning (ML) algorithm would not be as effective, since different PUFs instances will not share similar CRP sets. Our template attack only needs few CRPs for profiling (at most 170), but it can be applied to different instances without additional training, which Machile Learning cannot do with unbiased PUF instances.

Circumventing Uniqueness of XOR Arbiter PUFs

Phase-change memory (PCM) traz novos ensejos para industria eletronica. Devido as projecoes de alta escalabilidade do processo de fabricacao da PCM, cogita-se usa-la como memoria principal em sistemas de computacao, substituindo a tradicional DRAM cujos problemas de miniaturizacao do processo de fabricacao demandam tecnologias ainda desconhecidas. Contudo, PCM tem problemas de durabilidade e tecnicas de recuperacao de falhas robustas sao extremamente necessarias para recuperacao e prolongamento do seu tempo de vida, medido em numero de escritas. As tecnicas mais comuns de recuperacao de falhas sao os codigos de correcao de erros. Porem, outras tecnicas de recuperacao vem sendo propostas na literatura, aproveitando as caracteristicas de nao-volatilidade da PCM. Neste trabalho, usando uma modelagem matematica, analisou-se como a probabilidade de bit-ip dos principais codigos de correcao de erros { paridade, SECDED e BCH { e das principais tecnicas de recuperacao de falhas { ECP e SAFER { esta relacionada _a durabilidade da PCM. A partir da taxa de bit-ip medida atraves da execucao do SPEC2006 e por meio dos modelos matematicos, comparou-se os resultados dos modelos de simulacao utilizando-se a probabilidade teorica de 50% e a taxa obtida experimentalmente de 15%. Os resultados revelaram uma visivel degradacao da durabilidade dos mecanismos de recuperacao de falhas que usam codigos de correcao de erros, contradizendo os resultados da literatura. A tecnica ECP foi a unica que nao mostrou degradacao. Alem disso, uma analise de eficiencia energetica foi feita, relacionando durabilidade da PCM e o consumo de energia. Novamente, a tecnica ECP se destacou nos resultados, como tambem a tecnica SAFER. Finalmente, foram propostos modelos analiticos probabilisticos das tecnicas ECP, SECDED e uma analise da tecnica PAYG baseada no modelo analitico da ECP. 
Abstract

Análise de desgaste de técnicas de correção de erros em phase-change memories

The present invention relates to a secure architecture for authenticating and checking the integrity of cache memory lines using PUFs for embedded systems, and aims at preventing the insertion of malicious codes in these systems. Thus, the invention protects code and data integrity and makes it possible to detect any alteration of the programs in an embedded system (including the operating system, if available). The invention belongs to the field of computer systems, more specifically the architecture of embedded systems and information security.

Secure architecture for embedded systems

Phase-Change Memory (PCM) is new memory technology and a possible replacement for DRAM, whose scaling limitations require new lithography technologies. Despite being promising, PCM has limited endurance (its cells withstand roughly 108 bit-flips before failing), which prompted the adoption of Error Correction Techniques (ECTs). However, previous lifetime analyses of ECTs did not consider the difference between the bit-flip frequencies of data and code bits, which may lead to inaccurate wear-out analyses for the ECTs. In this work, we improve the wear-out analysis of PCM by modeling and analyzing the bit-flip probabilities of five ECTs. Our models also enable an accurate estimation of energy consumption and analysis of the endurance-energy trade-off for each ECT.

Wear-out analysis of error correction techniques in phase-change memory

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