The IEEE T RANSACTIONS ON C OMPUTER -A IDED D ESIGN OF I NTEGRATED C IRCUITS AND S YSTEMS publishes manuscripts focusing on methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, veriﬁcation, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.TheIEEE T RANSACTIONS ON C OMPUTER -A IDED D ESIGN OF I NTEGRATED C IRCUITS AND S YSTEMS is published by the IEEE Council on Electronic Design Au- tomation. The IEEE Council on Electronic Design Automation (CEDA) is an organizational unit of the IEEE that has six IEEE member societies, namely, Antennas and Propagation, Circuits and Systems, Computer, Electron Devices, Microwave Theory and Techniques, and the Solid-State Circuits Societies. The objectives of CEDA include fostering design automation of electronic circuits and systems at all levels, by means of publications, conferences/workshops and volunteer activities. For membership and subscription information and pricing, please visit www.ieee.org/membership-catalog. Member copies of Transactions/Journals are for personal use only.

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

Beyond Bias and Barriers : Fulfilling the Potential of Women in Academic Science and Engineering

Bypass the limitations of synchronous design and create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. The fundamentals of asynchronous design are covered, as is a large variety of design styles, while the emphasis throughout is on practical techniques and real-world applications.

/pdf/a-designer-s-guide-to-asynchronous-vlsi-1f20iy46zo.pdf

A Designer's Guide to Asynchronous VLSI

We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and show how asynchronous logic can efficiently take advantage of this large amount of pipelining. Our FPGA, which does not use a clock to sequence computations, automatically self-pipelines" its logic without the designer needing to be explicitly aware of all pipelining details. This property makes our FPGA ideal for throughput-intensive applications and we require minimal place and route support to achieve good performance. Benchmark circuits taken from both the asynchronous and clocked design communities yield throughputs in the neighborhood of 300--400 MHz in a TSMC 0.25m process and 500--700 MHz in a TSMC 0.18m process.

/pdf/highly-pipelined-asynchronous-fpgas-sh0bkhuljb.pdf

Highly pipelined asynchronous FPGAs

We discuss the design of a high-performance field programmable gate array (FPGA) architecture that efficiently prototypes asynchronous (clockless) logic. In this FPGA architecture, low-level application logic is described using asynchronous dataflow functions that obey a token-based compute model. We implement these dataflow functions using finely pipelined asynchronous circuits that achieve high computation rates. This asynchronous dataflow FPGA architecture maintains most of the performance benefits of a custom asynchronous design, while also providing postfabrication logic reconfigurability. We report results for two asynchronous dataflow FPGA designs that operate at up to 400 MHz in a typical TSMC 0.25 /spl mu/m CMOS process.

An asynchronous dataflow FPGA architecture

A self-timed programmable architecture used for the implementation of Phased Logic (PL) systems is described. PL systems are automatically translated from clocked designs and result in self-timed circuits that are insensitive to delays between gates. The target implementation is a self-timed FPGA architecture composed of PL gates. A PL gate design based on a 4-input lookup table is presented. Power and performance estimates of two designs are given and are compared to their clocked counterparts.

http://lyle.smu.edu/~mitch/ftp_dir/pubs/asic01.pdf

Cell designs for self-timed FPGAs

Data-dependent completion time is a well-known advantage of self-timed circuits, one that allows them to operate at average rather than worst-case execution rates. A technique called early evaluation (EE) that extends this advantage by allowing self-timed modules to produce results before all of their inputs have arrived is described here. The technique can be applied to any combinational function and is integrated into the phased logic (PL) design methodology that accepts synchronous design entry and produces delay-insensitive self-timed circuits. We describe an algorithm that ensures that the resulting delay-insensitive circuits are safe, and develop a generalized method for inserting EE gates into any PL netlist. We give performance results for several benchmark circuits, including a five-stage pipelined CPU and a microprogrammed floating-point unit. Comparisons are made among clocked circuits, PL circuits, and PL circuits with EE. Simulation results show a clear performance benefit for PL circuits that use EE.

Early evaluation for performance enhancement in phased logic

This paper describes an asynchronous design tool flow known as phased logic that converts a clocked design into an asynchronous design implemented as a micropipeline using two-phase control and bundled data signaling. Example designs include variations of a double-precision floating-point clipping operation mapped to two commercial standard cell libraries (0.18/spl mu/ and 0.13/spl mu/) and a five-stage pipelined MIPs-compatible integer unit mapped to the 0.13/spl mu/ library. The design style includes a feature known as early evaluation, which is a generalized form of bypass that allows the self-timed design to recover some of the inherent latch delay penalty in micropipelines.

A coarse-grain phased logic CPU

A five-stage pipelined CPU based on the MIPs ISA is mapped to a self-timed logic family known as Phased Logic (PL). The mapping is performed automatically from a netlist of D-Flip-Flops and 4-input Lookup Tables (LUT4s) to a netlist of Phased Logic gates. Each PL gate implements a 4-input Lookup Table in addition to control logic required for the PL control scheme. PL offers a speedup technique known as Early Evaluation that can be used to boost performance at the cost of additional PL gates. Several different PL gate-level implementations are produced to explore different architectural tradeoffs using early evaluation. Simulations run for five benchmark programs show an average speedup of 1.48 over the clocked netlist at the cost of 17% additional PL gates.

http://lyle.smu.edu/~mitch/ftp_dir/pubs/isvlsi03.pdf

A fine-grain Phased Logic CPU

Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have been applied to asynchronous circuits in the past in order to achieve throughput increases. A general method for computing early evaluation functions is presented for this design style. Experimental results are given that show the increase in throughput of various benchmark circuits. The results show that as much as a 30% speedup can be achieved in some cases.

/pdf/generalized-early-evaluation-in-self-timed-circuits-380mnr2mww.pdf

Generalized Early Evaluation in Self-Timed Circuits

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