A new mobility degradation specific to short channel MOSFETs is studied and elucidated. Pocket implants/dopants pile-up, interface states/oxide charges, remote Coulomb scattering or ballisticity are insufficient to explain this degradation. The role of non-Coulombian (neutral) defects, which can be healed by increasing the annealing temperature, is evidenced.

Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling

A simple analytical model that describes MOSFET operation in saturation from subthreshold to strong inversion is used to derive a new formulation of the intrinsic switching delay of the transistor. The proposed model follows the scaling trend of experimental ring-oscillator data better than the conventional CV/I metric. The historical trend of MOSFET performance scaling is examined, and it is shown that the continuous increase of the carrier velocity in the channel has been the main driver for the improved transistor performance with scaling. The dependence of velocity and mobility in recent strain-engineered devices is studied based on published experimental data, and a theory is proposed to justify this dependence. It is shown that the virtual-source velocity depends on low-field mobility more strongly than what was previously believed, in spite of the fact that state-of-the-art MOSFETs operate at 60%-65% of their ballistic limit. These observations will be used in Part II of this paper to explore the tradeoffs between key device parameters in order for the commensurate scaling of the device performance with its dimensional scaling to continue in the future high-performance CMOS generations.

MOSFET Performance Scaling—Part I: Historical Trends

The need for meeting the expectations of continuing the enhancement of CMOS performance and density has inspired the introduction of new materials into the classical single-gate bulk MOSFET and the development of nonclassical multigate transistors at an accelerated rate. There is a strong need to understand and model the associated new physics and electrical behavior to ensure widespread very-large-scale-integration circuit applications of new technologies. This paper presents some of the efforts toward the modeling of new technologies for bulk MOSFETs and multigate transistors. A holistic model for mobility enhancement through process-induced stress and a dynamic behavior model for high-k transistors have been developed to capture some of the new effects and new materials in the bulk MOSFET. A new analytical model is also presented for the fundamentally new device structure-FinFET

Modeling Advanced FET Technology in a Compact Model

Challenges and opportunities in advanced Ge pMOSFETs

Strain greatly affects the electrical properties of silicon because strain changes the energy band structure of silicon. In MOSFET devices, the terminal voltages induce electrical fields, which themselves modulate the electronic band structure and interact with strain-induced changes. Applied electrical fields are used to experimentally study different state-of-the-art local and global strain techniques and reveal the different responses of n- and p-MOSFETs to the different strain techniques. It is shown that p-MOSFETs have more low-lateral-field linear drive-current enhancement and less high-lateral-field saturation drive-current enhancement at both low and high vertical fields. The situation is similar for n-MOSFETs at low vertical fields. However, at high vertical fields, n-MOSFET low-lateral-field linear drive-current enhancement is less than the high-lateral-field saturation drive-current enhancement. The origin for this behavior can be found in the different strain effects on the electronic band structure, which results in effective mass reduction and/or scattering suppression. These, in turn, contribute differently to linear and saturation drive-current enhancements in n- and p-MOSFETs.

Understanding Strain-Induced Drive-Current Enhancement in Strained-Silicon n-MOSFET and p-MOSFET

We report a detailed comparison of low and high-Vd transport between various substrate- and process-induced strained MOSFETs down to 40nm gate lengths. Thanks to an original extraction method and low temperature measurements, we demonstrate that the mobility behaviour is deeply impacted by the down-scaling because of Coulomb scattering. Introducing this behaviour into a saturation current model, we clearly explain the I/sub ON/ enhancement trend of all strained devices.

Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs

This letter presents the first experimental study of the mobility in 50-nm gate length (L/sub G/) pMOSFETs highly strained by a contact etch stop layer. Thanks to an advanced characterization method, the mobility is in-depth studied versus the inversion charge density, the gate length and the temperature. The physical origin of the more than 50% mobility enhancement at L/sub G/=50 nm is proven to be the low effective mass of the top valence band rather than any scattering modification. This mobility gain is maintained even at high effective field. This explains the 30% I/sub ON/ enhancement at 50-nm gate length, which is among the best results at such a dimension.

In-depth characterization of the hole mobility in 50-nm process-induced strained MOSFETs

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Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs

In-depth characterization of the hole mobility in 50-nm process-induced strained MOSFETs