Introduction.- Boolean Functions.- Finite State Machine Based Approaches.- Propositional Temporal Logics.- Higher Order Logic.- Appendix.- References.- Index.A more detailed table of contents can be found on our web site: http://www.springer.de

Introduction to formal hardware verification

Evaluation and Improvements of Boolean Comparison Method Based on Binary Decision Diagrams

Regarding finite state machines as Markov chains facilitates the application of probabilistic methods to very large logic synthesis and formal verification problems. In this paper we present symbolic algorithms to compute the steady-state probabilities for very large finite state machines (up to 10/sup 27/ states). These algorithms, based on Algebraic Decision Diagrams (ADD's)-an extension of BDD's that allows arbitrary values to be associated with the terminal nodes of the diagrams-determine the steady-state probabilities by regarding finite state machines as homogeneous, discrete-parameter Markov chains with finite state spaces, and by solving the corresponding Chapman-Kolmogorov equations. We first consider finite state machines with state graphs composed of a single terminal strongly connected component; for this type of system we have implemented two solution techniques: One is based on the Gauss-Jacobi iteration, the other one is based on simple matrix multiplication. Then we extend our treatment to the most general case of systems which can be modelled as finite state machines with arbitrary transition structures; here our approach exploits structural information to decompose and simplify the state graph of the machine. We report experimental results obtained for problems on which traditional methods fail.

Markovian analysis of large finite state machines

A problem in technology mapping is that the quality of the final implementation depends significantly on the initially provided circuit structure. This problem is critical, especially for mapping with tight and complicated constraints. In this paper, we propose a procedure which takes into account a large number of circuit structures during technology mapping. A set of circuit structures is compactly encoded in a single graph, and the procedure dynamically modifies the set during technology mapping by applying simple local transformations to the graph. State-of-the-art technology mapping algorithms are naturally extended, so that the procedure finds an optimal tree implementation over all of the circuit structures examined. We show that the procedure effectively explores the entire solution space obtained by applying algebraic decomposition exhaustively. However, the run time is proportional to the size of the graph, which is typically logarithmic in the number of circuit structures encoded. The procedure has been implemented and used for commercial design projects, We present experimental results on benchmark examples to demonstrate its effectiveness.

/pdf/logic-decomposition-during-technology-mapping-4nw99nxmje.pdf

Logic decomposition during technology mapping

There is a growing need for reliable methods of designing correct reactive systems such as computer operating systems and air traffic control systems. It is widely agreed that certain formalisms such as temporal logic, when coupled with automated reasoning support, provide the most effective and reliable means of specifying and ensuring correct behavior of such systems. This paper discusses known complexity and expressiveness results for a number of such logics in common use and describes key technical tools for obtaining essentially optimal mechanical reasoning algorithms. However, the emphasis is on underlying intuitions and broad themes rather than technical intricacies.

Automated temporal reasoning about reactive systems

A theory of sequential hardware equivalence is presented. This theory includes the notions of gate-level model (GLM), hardware finite state machine (HFSM), quotient machine, state equivalence ( approximately ), alignability, resetability, essential resetability, isomorphism, and sequential hardware equivalence. The theory is motivated by (1) the observation that it is impossible to control the initial state of a machine when it is powered on and (2) the desire to decide equivalence of two designs based solely on their netlists and logic device models, without knowledge of intended initial states or intended environments. Algorithms based upon a binary decision diagram (BDD) implementation of predicate calculus over Boolean domains are presented. This calculus is employed to calculate properties of hardware designs. Experimental results based upon these algorithms as implemented in the MCC sequential equivalence tool (SET) are presented. >

A theory and implementation of sequential hardware equivalence

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A theory and implementation of sequential hardware equivalence