C. Leroux
STMicroelectronics
33 Papers
233 Citations
C. Leroux is an academic researcher from STMicroelectronics. The author has contributed to research in topics: Gate oxide & High-κ dielectric. The author has an hindex of 9, co-authored 33 publications.
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Papers
Characterization of effective mobility by split C(V) technique in N-MOSFETs with ultra-thin gate oxides
TL;DR: In this article, the amplitude of the effective mobility is found to be degraded significantly with oxide scaling, and the mobility attenuation at high field associated to the surface roughness remains unchanged with oxide thickness reduction.
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Electrical and physico-chemical characterization of HfO2/SiO2 gate oxide stacks prepared by atomic layer deposition
J.-F. Damlencourt,O. Renault,D. Samour,A.M. Papon,C. Leroux,François Martin,S. Marthon,M. N. Séméria,X. Garros +8 more
TL;DR: In this paper, correlated electrical measurements of thin HfO2 layers deposited on SiO2 by atomic layer deposition with angle-resolved X-ray photoelectron spectroscopy experiments were obtained.
46
Automatic statistical full quantum analysis of C-V and I-V characteristics for advanced MOS gate stacks
TL;DR: In this paper, a global methodology for automatic and reliable extraction of VFB (Flat Band Voltage), EOT( Equivalent Oxide thickness) and leakage current at referenced biases (constant bias offsets from VFB or Vt, the threshold voltage) on advanced gate stacks is presented.
23
Investigating doping effects on high-κ metal gate stack for effective work function engineering
C. Leroux,S. Baudot,Mathieu Charbonnier,A. Van Der Geest,P. Caubet,A. Toffoli,P. Blaise,Gerard Ghibaudo,F. Martin,G. Reimbold +9 more
TL;DR: In this paper, the impact of additive at the SiO2/high-κ interface has been investigated through ab initio simulations and electrical measurements, and various gate stacks with additive below or the above high-κ dielectric are compared.
18
Characterization and modeling of nanometric SiO 2 dielectrics
TL;DR: In this paper, the limit of characterization and modeling of nanometric oxide is investigated on two different lots, with targeted oxide thickness from 3.5 to 0.6 nm, and electrical characterizations are firstly evaluated in regard to targeted oxide, then, thickness obtained through quantum modeling are compared to other physical measurements.
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