Caches consume a significant amount of energy in modern microprocessors. To design an energy-efficient microprocessor, it is important to optimize cache energy consumption. This paper examines performance and power trade-offs in cache designs and the effectiveness of energy reduction for several novel cache design techniques targeted for low power.

/pdf/cache-design-trade-offs-for-power-and-performance-1eitlwsgnf.pdf

Cache design trade-offs for power and performance optimization: a case study

In microprocessor-based systems, large power savings can be achieved through reduction of the transition activity of the on- and off-chip buses. This is because the total capacitance being switched when a voltage change occurs on a bus line is usually sensibly larger than the capacitive load that must be charged/discharged when internal nodes toggle. In this paper, we propose an encoding scheme which is suitable for reducing the switching activity on the lines of an address bus. The technique relies on the observation that, in a remarkable number of cases, patterns traveling onto address buses are consecutive. Under this condition it may therefore be possible, for the devices located at the receiving end of the bus, to automatically calculate the address to be received at the next clock cycle; consequently, the transmission of the new pattern can be avoided, resulting in an overall switching activity decrease. We present analytical and experimental analyses showing the improved performance of our encoding scheme when compared to both binary and Gray addressing schemes, the latter being widely accepted as the most efficient method for address bus encoding. We also propose power and timing efficient implementations of the encoding and the decoding logic, and we discuss the applicability of the technique to real microprocessor-based designs.

Asymptotic zero-transition activity encoding for address buses in low-power microprocessor-based systems

/pdf/asymptotic-zero-transition-activity-encoding-for-address-2p707bg9ck.pdf

Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems

We survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered.

/pdf/a-survey-of-optimization-techniques-targeting-low-power-vlsi-42nf4kr6lf.pdf

A Survey of Optimization Techniques Targeting Low Power VLSI Circuits

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

CMOS circuits consume power during the charging and discharging of capacitances. Reducing switching activity then, saves power in embedded processors. The authors' two-pronged attack uses Gray code addressing and cold scheduling to eliminate bit switches. >

Saving power in the control path of embedded processors

Abstract Pedigree analysis was performed in three major Taiwanese swine breeds to evaluate the genetic variability in the current population and determine the main reason for genetic diversity (GD) loss after the occurrence of foot-and-mouth disease (FMD) in Taiwan. The pedigree files of the Duroc, Landrace, and Yorkshire breeds, containing 60,237, 87,177, and 34,373 records, respectively, were analyzed. We divided the population into two subpopulations (pre-1998 and post-1998) to determine the role of FMD in GD loss. Pedigree completeness and related indicators were analyzed to evaluate the pedigree quality, and several parameters were used to measure the levels of GD and further used to determine the major cause of GD loss. The pedigree completeness indexes for the different breeds were higher than 0.60, and the trend was enhanced after the FMD outbreak. The estimated proportion of random genetic drift in GD loss increased in all breeds over time (from 62.64% to 78.44% in Duroc; from 26.26% to 57.99% in Landrace; and from 47.97% to 55.00% in Yorkshire, respectively). The effective population size of Duroc and Landrace were increased by the time (Duroc: from 61.73 to 84.75; Landrace: from 108.70 to 113.64); however, it shows opposite trend in Yorkshire population (decline from 86.21 to 50.00). In summary, the occurrence of FMD led to the major loss of GD loss by random genetic drift. Therefore, for the recovery of GD, breeders in Taiwan should increase the effective population size with newly imported genetic materials and adjust the breeding strategy to reduce the inbreeding rate.

/pdf/pedigree-based-analyses-of-changes-in-genetic-variability-in-1akwlt5d.pdf

Pedigree-based analyses of changes in genetic variability in three major swine breeds in Taiwan after a disease outbreak

The objective of this study is to establish a model suitable for the Dairy Herd Improvement (DHI) records under tropical/subtropical climate in Taiwan. There are 62,068 lactation records of 28,722 cows obtained from Taiwan the DHI program during 2009~2019. A model with the physical situation of lactation (PSL) as a fixed effect which accounts for abnormal physiology and subclinical mastitis is compared to a model without that effect. The heritability of milk yield and somatic cell score are decreased and the number of sires with the accuracy of estimated breeding values greater than 75% would also change in the model with PSL as a fixed effect. Moreover, AIC and BIC in the model with PSL are lower than the model without PSL, which indicates the former model is more appropriate for this DHI dataset. 

665. Comparison of two models for dairy herd improvement data in Taiwan

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Saving power in the control path of embedded processors

Pedigree-based analyses of changes in genetic variability in three major swine breeds in Taiwan after a disease outbreak

665. Comparison of two models for dairy herd improvement data in Taiwan