Thin-wafer handling is one of the key enabling technologies for 2.5D/3D IC integration. Usually, it temporary bonds the TSV (through-silicon via)/RDL (redistribution layer) wafer (e.g., passive and active interposers) to a supporting carrier wafer with an adhesive, backgrinds the TSV/RDL interposer wafer to very thin (≤100μm), goes through all the necessary processes, and then de-bonds the thin TSV/RDL interposer wafer from the carrier wafer. In this study, a different route will be taken which eliminates the temporary bonding and de-bonding processes. Emphasis is placed on using a heat-spreader wafer as a supporting carrier wafer during the manufacturing processes and after the assembly is completed (diced), the heat-spreader remains on the thin TSV/RDL interposer. This is a very simple and low-cost thin-wafer handling method for 2.5D/3D IC integration.

Thin-Wafer Handling with a Heat-Spreader Wafer for 2.5D/3D IC Integration

Wafer level molding is an important process step in the chip on wafer approach and seems currently required in stacking first process flow. Thermo-mechanical properties of molding material has to be controlled to limit stress induce by CTE mismatch with silicon wafer and also to assure planarization and protection functions. 2D and 3D finite element simulations have been performed to evaluate strain and stress impact at wafer level of material properties of silicone based and epoxy based molding compounds. Impacts of Si interposer thickness, design and chips arrangement on wafer warpage are presented and compared with experimental results.

Wafer level encapsulated materials evaluation for chip on wafer (CoW) approach in 2.5D Si interposer integration

This paper focuses on the application of low temperature bonding to the fabrication of three-dimensional (3D) massively parallel signal processors for high performance infrared imagers. We review two generations of the 3D heterogeneous integration process. The first generation process, compatible with pixel sizes in the 20 to 30 µm range, relies on low temperature epoxy bonding that is followed by the formation of copper-filled through-silicon vias (TSVs). The second generation process, scalable to pixel sizes of 10 µm and smaller, employs solid–liquid diffusion bonding of copper–tin to copper at 250 °C; the bonding follows TSV fabrication. To demonstrate the second generation process, we fabricated 3D test vehicles in the form of 640 × 512 arrays of vertical interconnects composed of TSVs and metal–metal bonds on a 10 µm pitch. We characterized electrical conductivity of the interconnects, the isolation resistance between the interconnects, and the operability and yield of the arrays. The successful demonstration of the interconnect technology paves the way to a functional demonstration of 3D signal processors in infrared imagers with 10 µm pixels.

https://iopscience.iop.org/article/10.7567/JJAP.54.030202/pdf

Scaling of three-dimensional interconnect technology incorporating low temperature bonds to pitches of 10 µm for infrared focal plane array applications

Wafer thinning represents a critical step in 2.5D and 3D-IC integration. Achieving low total thickness variation (TTV) of a bonded stack is essential since it directly impacts the TTV of the thinned device wafer. It is essential to understand and utilize appropriate processes and materials that provide precision bonded stacks prior to thinning operations in order to achieve high process yields. The 3M™ Wafer Support System and Corning's precision glass carrier wafers were used to produce bonded stacks. Leveraging metrology tools like the Flatmaster MSP-300 and low coherence interferometric probes allow for characterization of the TTV of each layer of a bonded stack and better understanding of the stack-up as well as how to minimize stack TTV. The ability to deliver stack TTV of < 2 um in a repeatable manner has been demonstrated.

Production Proven, High Precision Temporary Bond/De-bond Process

With the strong grow of smartphone, wearable devices and the upcoming IoT in our life. Wafer level packages offer the lowest total cost of higher semiconductor content with leveraging the smallest die size and the highest performing, most reliable on the market today. The existing testing process of WLPs encounter the new challenges from thinner and warpage wafers which will impact high parallelism multi-sites testing performance and KGDs of wafer singulation.

Advanced multi-sites testing methodology after wafer singulation for WLPs process

Three-dimensional (3D) stacked IC technologies have become a central topic over the past few years, and start to become reality with the introduction of 3D devices in commercialization Among the technical challenges raised by this technology, thin wafer handling remains one of the most challenging A large number of publications have focused on this process since several years to present the performances of the different competitors The goal of this paper is to discuss the 300mm interposer creation process using 2 of the most spread temporary bonding techniques: ZoneBOND™ and WSS (Wafer Support System) The comparison will be achieved during the different process steps considering 50μm or 80μm thick silicon interposers The comparison will be done considering the 2 major challenges of temporary bonding integration: interposer flatness control and stability during the backside process Finally this work has enabled us to identify the drawbacks and advantages of each technique for 3D integration

WSS and ZoneBOND temporary bonding techniques comparison for 80μm and 55μm functional interposer creation

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WSS and ZoneBOND temporary bonding techniques comparison for 80μm and 55μm functional interposer creation