The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

http://science.sciencemag.org/content/sci/311/5758/208.full.pdf

Stretchable form of single crystal silicon for high performance electronics on rubber substrates

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Methods and devices for fabricating and assembling printable semiconductor elements

A process for etching a substrate 25 in an etching chamber 30, and simultaneously cleaning a thin, non-homogeneous, etch residue deposited on the surfaces of the walls 45 and components of the etching chamber 30. In the etching step, process gas comprising etchant gas is used to etch a substrate 25 in the etching chamber 30 thereby depositing etch residue inside the chamber 30. Cleaning gas is added to the process gas for a sufficient time and in a volumetric flow ratio that is sufficiently high, to react with and remove substantially all the etch residue deposited by the process gas. The present method advantageously cleans the etch residue in the chamber 30, during the etching process, and without use of separate cleaning, conditioning, and seasoning process steps.

Self-cleaning etch process

A process for etching a substrate and removing etch residue deposited on the surfaces in the etching chamber has two stages. In the first stage, an energized first process gas is provided in the chamber, and in the second stage, an energized second process gas is provided in the chamber. The energized first process gas comprises SF 6 and Ar, the volumetric flow ratio of SF 6 to other components of the first process gas being from about 5:1 to about 1:10. The energized second process gas comprises CF 4 and Ar, the volumetric flow ratio of CF 4 to other components of the second process gas being from about 1:0 to about 1:10.

Two-stage etching process

In preferred embodiments, a polydentate pore-sealing ligand is used to seal or repair pores damaged by plasma processing. The polydentate ligand includes bidentate ligands corresponding to the general formula X—CH 2 —(CH 2 ) n —CH 2 —X or X—Si(CH 3 ) 2 —(CH 2 ) n —Si(CH 3 ) 2 —X. The polydentate ligand also includes tridendate ligands corresponding to the general formula X—CH 2 —(CH 2 ) m (CXH)(CH 2 ) o —CH 2 —X or X—Si(CH 3 ) 2 —(CH 2 ) m (CXH)(CH 2 ) o —Si(CH 3 ) 2 —X. Alternative embodiments may include single or multiply branched polydentate ligands. Other embodiments include ligands that are cross-linked after attachment to the dielectric. Still other embodiments include a derivatization reaction wherein silanol groups formed by plasma damage are removed and favorable dielectric properties are restored.

Using polydentate ligands for sealing pores in low-k dielectrics

A method in a plasma processing chamber for etching through a selected portion of a layer stack. The layer stack comprises a metallization layer, a first barrier layer disposed adjacent to the metallization layer, and a photoresist layer disposed above the metallization layer. The method includes etching at least partially through the first barrier layer using a high sputter component etch. The method further includes etching at least partially through the metallization layer using a low sputter component etch. The low sputter component etch has a sputter component lower than a sputter component of the high sputter component etch.

Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing

RIE of metallization is achieved at low power and low pressure using Cl 2 and HCl as reactant species by creating a transformer coupled plasma with power applied to electrodes positioned both above and below a substrate with metallization thereon to be etched. Three layer metallizations which include bulk aluminum or aluminum alloy sandwiched between barrier layers made from, for example, Ti/TiN, are etched in a three step process wherein relatively lower quantities of Cl 2 are used in the plasma during etching of the barrier layers and relatively higher quantities of Cl 2 are used during etching of the bulk aluminum or aluminum alloy layer. The ratio of etchants Cl 2 and HCl and an inert gas, such as N 2 are controlled in a manner such that a very thin side wall layer (10-100 Å) of reaction byproducts created during RIE are deposited on the side walls of trenches formed in the metallization during etching. The side wall layer improves the isotropic nature of the etch such that submicron metallization lines with defect free side walls are formed. Hydrogen (H 2 ) can be added to the plasma and will act to reduce corrosion.

Low pressure and low power C12 /HC1 process for sub-micron metal etching

Metal silicide is removed at a faster rate than polysilicon in dry etching of metal silicide/polysilicon composites with an etching gas made from HCl and Cl2 at a volumetric flowrate ratio of HCl:Cl2 within the range of 3:1 to 5:1.

Polycide etching with HCL and chlorine

A method is provided for forming a step in a layer of material (16). The method includes forming the layer over a substrate. A cavity (24) is formed in a portion of an upper surface of the layer. The formed cavity is filled with a filler material (26) to provide a substantially planar surface over the substrate. A photoresist layer is formed over the substantially planar surface over the substrate. An aperture (30) is formed in the photoresist layer in registration with the formed cavity. The aperture exposes a portion of the filler material. The exposed portion (32) of the filler material is removed along with a contiguous portion of the layer (16) to form the step in the indentation. The cavity may be either a trench or a via. A 'Trench First' approach and a 'Via First' approach are described.

Method for forming dual damascene structure

PROBLEM TO BE SOLVED: To make more vertical sidewall shape while reducing the corrosion by a method wherein aluminum and aluminum alloy are anisotropically etched away by RIE using specific low power and pressure. SOLUTION: In the title process, aluminum and aluminum alloy are anisotropically etched away by RIE using low power (not exceeding 350W) and low pressure (not exceeding 15mT). Within an upper layer 14 and a bottom layer 10, the physical etching process called sputtering is performed while in a bulk aluminum layer 12, the chemical process is performed. As for the reaction gas of RIE, chlorine, HCl and inert gas (e.g. nitrogen, argon, helium, etc.) are enumerated. Through these procedures, the corrosion of sidewall and the other problems posed by high power RIE can be solved. Besides, a photoresist 16 can be removed more easily while it is released.

Low pressure low power chlorine/hydrogen chloride process for submicron metal etching

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