A system for decoding guest instructions includes an emulation routine store in host processor addressable memory having a set of emulation programs beginning at corresponding emulation program addresses. A sequence of guest instructions is stored in the host processor addressable memory, and logic is provided which retrieves a current guest instruction in the sequence and jumps directly to an emulation program address in response to the current guest instruction. The emulation routine store is optimized by dividing it into a dispatch table having a set of dispatch entries and an emulation routine store storing a set of emulation entries. Each dispatch entry includes a plurality of host instructions of the emulation program corresponding to a particular guest instruction. The plurality of host instructions in a dispatch entry includes a host jump instruction which causes a jump to an emulation entry. The emulation entry stores a host instruction routine which includes host instructions to decode and prefetch guest instructions to form an emulation program address to a dispatch entry for a next guest instruction, and to jump directly to the dispatch entry.

Decoding guest instruction to directly access emulation routines that emulate the guest instructions

The Art of Readable Writing

The progress of the semiconductor industry over the last several decades has been described as a series of alternating cycles of standardization and customization. According to Makimoto’s wave, as the model is known, we are now in an era of field programmability. This cycle is characterized by standardization in manufacturing and customization in application. The application drivers for this second digital wave are networking, digital consumer electronics and the convergence of communications and computing technologies. Xilinx has been the foremost company in field programmable logic since inventing the FPGA over twenty years ago. Today, Xilinx FPGAs are the key technology enabling the era of programmability. From this vantage point, we begin this talk by surveying the key technologies that define the state-of-the-art in field programmable logic. We proceed to explore future directions and consider some of the most important research challenges that lie ahead. Solutions to the research challenges will require the best efforts of many talented minds around the world. Continued collaboration between academia and industry is vital at the graduate research level. Equally important is the need to ensure that young engineers are adequately prepared for the era of programmability. We close by describing some of the novel work emerging from Xilinx research and the initiatives that we are taking to ensure the ongoing success of our partnership with academia worldwide.

Field Programmable Logic and Application

The CISC architecture is extended to provide for segments that can hold RISC code rather than just CISC code. These new RISC code segments have descriptors that are almost identical to the CISC segment descriptors, and therefore these RISC descriptors may reside in the CISC descriptor tables. The global descriptor table in particular may have CISC code segment descriptors for parts of the operating system that are written in x86 CISC code, while also having RISC code segment descriptors for other parts of the operating system that are written in RISC code. An undefined or reserved bit within the descriptor is used to indicate which instruction set the code in the segment is written in. An existing user program may be written in CISC code, but call a service routine in an operating system that is written in RISC code. Thus existing CISC programs may be executed on a processor that emulates a CISC operating system using RISC code. A processor capable of decoding both the CISC and RISC instruction sets is employed. The switch from CISC to RISC instruction decoding is triggered when control is transferred to a new segment, and the segment descriptor indicates that the code within the segment is written in the alternate instruction set.

Emulating operating system calls in an alternate instruction set using a modified code segment descriptor

A dual-instruction-set CPU is able to execute x86 CISC (complex instruction set computer) code or PowerPC RISC (reduced instruction set computer) code Three modes of operation are provided: CISC mode, RISC mode, both called user modes, and emulation mode Emulation mode is entered upon reset, and performs various system checks and memory allocation A special emulation driver is loaded into a portion of main memory set aside at reset Software routines to emulate the more complex instructions of the CISC architecture using RISC instructions are also loaded into the emulation memory A TLB is enabled, and translation tables and drivers are set up in the emulation memory All TLB misses, even in the user modes, will cause entry to a translator driver in emulation mode Since the TLB is always enabled for the user modes, and all misses are handled by the emulation code, the emulation code can set aside a portion of memory for itself and insure that the user programs never have access to the emulation memory Thus the programs, including operating systems, in CISC or RISC mode are unaware of emulation memory or even the existence of emulation mode

Dual-instruction-set architecture CPU with hidden software emulation mode

The Rise of Reconfigurable Systems.

A microprocessor chip which is capable of executing a specific subset of instructions on behalf of the main storage portion of a computer memory can be made to emulate direct execution instructions not in that specific subset while working on behalf a control storage portion of the computer memory in a manner which is transparent to the main storage portion by means of a novel set of operand space selection instructions in the control storage portion and a novel switching circuit on the microprocessor chip which controls the access of the chip to the control store portion and the main store portion.

Microprocessor implemented data processing system capable of emulating execution of special instructions not within the established microprocessor instruction set by switching access from a main store portion of a memory

The introduction of the microprocessor in 1971 marked the beginning of a 30-year stall in design methods for electronic systems. The industry is coming out of the stall by shifting from programmed to reconfigurable systems. In programmed systems, a linear sequence of configuration bits, organized into blocks called instructions, configures fixed hardware to mimic custom hardware. In reconfigurable systems, the physical connections among logic elements change with time to mimic custom hardware. The transition to reconfigurable systems will be wrenching, but this is inevitable as the design emphasis shifts from cost performance to cost performance per watt. Here’s the story.

The Inevitability of Reconfigurable Systems: The transition from instruction-based to reconfigurable circuits will not be easy, but has its time come?

The article discusses why only programmable handheld devices can do the job of any 10 different gizmos. The development of a chameleon-like handheld device is also described. The programmable logic device (PLD), a semiconductor containing a personalization memory and logic elements, can make it possible to have a pocket-electronics device consolidated with a number of features including adaptability to any network, capability to fit new standards, and having an upgradeable security system for the latest virus. Conventional PLDs are big, slow, power hungry, and expensive, but, like the microprocessors, PLDs can evolve in time into higher-level logic primitives that make them suitable for untethered applications.

Special report: go reconfigure

Subtle humor fosters learning through tongue-in-cheek advice on transforming simple, clear writing into technical papers appropriately complicated for the experienced scientist or engineer. Sophisticated, computer-based templates are being designed with passive-voice construction, repetition of ideas, and other features of scientific papers so that authors will need only to supply topical nouns to a computer in an interactive session to produce a paper written for their peers.

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