Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration [1–4], but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM (see Fig. 10.6.1). Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5×5mm2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm2 power density. The core architecture is developed from scratch to benefit from single-cycle access to SRAM.

3D-MAPS: 3D Massively parallel processor with stacked memory

This paper studies various design tradeoffs existing in the monolithic 3D integration technology. Different design styles in monolithic 3D ICs are studied, including transistor-level monolithic integration (MI-TR) and gate-level integration (MI-G). GDSII-level layout of monolithic 3D designs are constructed and analyzed. Compared with its 2D counterparts, MI-TR designs have advantages in footprint area, wire-length, timing, and power, because of the smaller footprint. MI-G design style also demonstrate advantages in area, timing and power over TSV-based designs, because of the smaller size and parasitics of inter-tier vias compared with TSVs. To further take the advantage of monolithic 3D technology, several technology improvement options are also explored. Besides, some possible design challenges with monolithic 3D are also studied, including global variation and signal integrity issues.

http://www.gtcad.gatech.edu/www/papers/06187545.pdf

A design tradeoff study with monolithic 3D integration

Three-dimensional network-on-chips are suitable communication fabrics for high-density 3D many-core ICs. Such networks have shorter communication hop count, compared to 2D NoCs, and enjoy fast and power efficient TSV wires in vertical links. Unfortunately, the fabrication process of TSV connections has not matured yet, which results in poor vertical links yield. In this work, we address this challenge and introduce AFRA, a deadlock-free routing algorithm for 3D mesh-based NoCs that tolerates faults on vertical links. AFRA is designed to be simple, high performance, and robust. The simplicity is achieved by applying ZXY and XZXY routings in the absence and presence of fault, respectively. Furthermore, AFRA, as will be proved, is deadlock-free when all vertical faulty links have the same direction. This enables the routing to save virtual channels for performance rather than scarifying them for deadlock avoidance. Finally, AFRA provides robustness, which means supporting connection for all possible pairs of communicating nodes in high fault rates. AFRA is evaluated, though cycle accurate network simulation, and is compared with planar adaptive routing. Results reveal that AFRA significantly outperforms planar adaptive routing in both synthetic and real traffic patterns. In addition, the robustness of AFRA is calculated analytically.

AFRA: A low cost high performance reliable routing for 3D mesh NoCs

AFRA: a low cost high performance reliable routing for 3D mesh NoCs

Since re-designing and re-optimizing existing logic, memory, and IP blocks in a 3D fashion significantly increases design cost, near-term three-dimensional integrated circuit (3D IC) design will focus on reusing existing 2D blocks. One way to reuse 2D blocks in the 3D IC design is to first perform 3D floorplanning, insert signal through-silicon vias (TSVs) for 3D inter-block connections, and then route the blocks. In this paper, we propose algorithms (finding signal TSV locations, assigning TSVs to whitespace blocks, and manipulating whitespace blocks) for post-floorplanning signal TSV planning in the block-level 3D IC design. Experimental results show that our signal TSV planner outperforms the state-of-the-art TSV-aware 3D floorplanner by 7% to 38% with respect to wirelength. In addition, our multiple TSV insertion algorithm outperforms a single TSV insertion algorithm by 27% to 37%.

https://eecs.wsu.edu/~daehyun/pubs/2012/2012aspdac.pdf

Block-level 3D IC design with through-silicon-via planning

We describe the design and analysis of 3D-MAPS, a 64-core 3D-stacked memory-on-processor running at 277 MHz with 63 GB/s memory bandwidth, sent for fabrication using Tezzaron's 3D stacking technology. We also describe the design flow used to implement it using industrial 2D tools and custom add-ons to handle 3D specifics.

/pdf/design-and-analysis-of-3d-maps-a-many-core-3d-processor-with-vroq2ab3iw.pdf

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory

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Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory