Semiconductor nanowires have been the subject of intensive research investment over the past few decades. Their physical properties afford them applications in a vast network of active microelectronic research fields, including logic device scaling in very large scale integrated circuits, sensor devices, and energy harvesting. A range of routes to semiconductor nanowire production have opened up as a result of advances in nanowire fabrication techniques over the last number of decades. These nanowire fabrication routes can usually be categorized into one of two paradigms, bottom-up or top-down. Microelectronic systems typically rely on integrated device platforms, where each device and component thereof can be individually addressed. This requirement for precise addressability places significant demands on the mode of fabrication, specifically with regard to device definition, placement and density, which have typically been strengths of top-down fabrication processes. However, in recent years, advances i...

Semiconductor Nanowire Fabrication by Bottom-Up and Top-Down Paradigms

Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

Electronic devices and systems, and methods for making and using the same

A field effect transistor includes a body layer having a strained crystalline semiconductor channel region, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer that is lattice mismatched with the channel region, and a crystalline gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed.

Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same

A field effect transistor (FET) includes a nanosheet stack having first and second stacked semiconductor channel layers. The first channel layer defines a channel region of a tunnel FET, and the second channel layer defines a channel region of a thermionic FET. Source and drain regions are provided on opposite sides of the nanosheet stack such that the first and second channel layers extend therebetween. A first portion of the source region adjacent the first channel layer and a second portion of the source region adjacent the second channel layer have opposite semiconductor conductivity types. Related fabrication and operating methods are also discussed.

Thermionically-overdriven tunnel FETs and methods of fabricating the same

The fabrication of an ultrathin Ge-rich SiGe body on silicon on insulator (SOI) is highly challenging for the next generation of fully depleted complementary metal-oxide semiconductor devices that will be implemented in the near future. Ge-rich layers (GRLs) could be fabricated using a Ge enrichment process which takes place during dry thermal oxidation of SiGe thin films. While several studies make use of the GRL for many applications, the basic mechanism at work during the enrichment process is still unclear. In this study, we address the mechanism of formation of GRL and we determine the major driving forces of the enrichment process. We highlight the particular role played by the Si0.5Ge0.5 which is stabilized for various experimental conditions and strain levels. A systematic study demonstrates that the 50% Ge content is stabilized by a self-limited interdiffusion process regulated by the entropic term of the formation energy, which is a minimum at Si0.5Ge0.5 at the expense of the elasticity-driven i...

/pdf/kinetics-and-energetics-of-ge-condensation-in-sige-oxidation-3kcepqwekj.pdf

Kinetics and Energetics of Ge Condensation in SiGe Oxidation

Horizontal and vertical tunneling field-effect transistors (TFETs) having an abrupt junction between source and drain regions increases probability of direct tunneling of carriers (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction. The abrupt junction may be formed by placement of a dielectric layer or a dielectric layer and a semiconductor layer in a current path between the source and drain regions. The dielectric layer may be a low permittivity oxide such as silicon oxide, lanthanum oxide, zirconium oxide, or aluminum oxide.

Tunneling field-effect transistor with direct tunneling for enhanced tunneling current

We report on the promise of dual channel materials using FinFETs for high-performance CMOS for sub 22 nm technology node. We demonstrate pFinFETs with all SiGe channel formed by Germanium condensation onto a Silicon-On-Insulator carrier wafer (SiGeOI) followed by cMOS processing. The devices exhibit 3.6X hole mobility enhancement over Silicon (100) while allowing for V TH control with single high-k and metal gate stack. These attributes taken together constitute a simple non-planar cMOS integration sequence with enhanced drive current for future high performance technology nodes.

Dual channel FinFETs as a single high-k/metal gate solution beyond 22nm node

A semiconductor structure may include a semiconductor bulk region with a gate stack on the semiconductor bulk region. The source region and the drain region in the semiconductor bulk region may be located on opposing sides of a channel region below the gate stack. An interfacial layer coupled to the channel region may modify a workfunction of a metal-semiconductor contact. In a MOSFET, the metal-semiconductor contact may be between a metal contact and the source region and the drain region. In a Schottky barrier-MOSFET, the metal-semiconductor contact may be between a silicide region in the source region and/or the drain region and the channel region. The interfacial layer may use a dielectric-dipole mitigated scheme and may include a conducting layer and a dielectric layer. The dielectric layer may include lanthanum oxide or aluminum oxide used to tune the workfunction of the metal-semiconductor contact.

Interfacial Barrier for Work Function Modification of High Performance CMOS Devices

We have developed a novel dual phase-modulated Ni silicide for Schottky barrier and series resistance reduction in dopant-segregated source/drain (DSS) n-MOSFETs. Using pre-silicide N2 + implant (thereafter N-implant), it is possible to selectively form interfacial epitaxial Si-rich NiSi2, reducing electron Schottky barrier(SB) from 0.7 eV to 0.34 eV while maintaining a low resistive bulk NiSi, at the same silicide formation temperature. Dual phase-modulated NiSi shows enhanced thermal stability up to 750degC, low rhos of 26 muOmegacm and SB modulation DeltaphiBn = 0.36 eV (expected 81% reduction in contact resistance Rc). Saturation gm for phase-modulated N-modulated DSS n-FETs shows 32% improvement over control NiSi with 22% reduction in series resistance Rext, while still maintaining CMOS integratability.

Selective phase modulation of NiSi using N-ion implantation for high performance dopant-segregated source/drain n-channel MOSFETs

Omega gate type pFETs with SiGe shell-Si core are demonstrated that show 30% mobility enhancement for (110) oriented fins and 46% mobility enhancement for (100) oriented fins compared to Si omega gate devices. Performance improvement is demonstrated because of higher mobility and inherent epitaxial strain, while the external resistance in the two SiGe and Si omega FETs is comparable. Performance can further be improved by uniaxial compressive stress.

High mobility SiGe shell-Si core omega gate pFETS

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