The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user friendliness of shared memory on the one side, and memory access scalability and efficiency on the other side. However, to get high performance out of such machines requires a dynamic mapping of application tasks and data onto the underlying architecture. Moreover, depending on the application behavior, this mapping should favor cache affinity, memory bandwidth, computation synchrony, or a combination of these. The great challenge is then to perform this hardware-dependent mapping in a portable, abstract way. To meet this need, we propose a hierarchical approach to the execution of OpenMP threads onto multicore machines. Our ForestGOMP runtime system dynamically generates structured trees out of OpenMP programs. It collects relationship information about threads and data as well. This information is used together with scheduling hints and hardware counter feedback by the scheduler to select the most appropriate threads and data distribution. ForestGOMP features a highlevel platform for developing and tuning portable threads schedulers. We present several applications for which we developed specific scheduling policies that achieve excellent speedups on 16-core machines.

/pdf/structuring-the-execution-of-openmp-applications-for-5cu4bkobiy.pdf

Structuring the execution of OpenMP applications for multicore architectures

We used the Spin model checker to show that Intel's implementation of software transactional memory is correct  Transactional memory makes it possible  to write properly-synchronized multi-threaded programs without the explicit use of locks We describe our model of Intel's implementation, our experience with Spin,  what we have shown, and what obstacles remain to showing more

/pdf/model-checking-transactional-memory-with-spin-c7iux7mzev.pdf

Model Checking Transactional Memory with Spin

Execution of applications on upcoming high-performance computing (HPC) systems introduces a variety of new challenges and amplifies many existing ones. These systems will be composed of a large number of “fat” nodes, where each node consists of multiple processors on a chip with symmetric multithreading capabilities, interconnected via high-performance networks. Traditional system software for parallel computing considers these chip multiprocessors (CMPs) as arrays of symmetric multiprocessing cores, when in fact there are fundamental differences among them. Opportunities for optimization on CMPs are lost using this approach. We show that support for fine-grained parallelism coupled with an integrated approach for scheduling of compute and communication tasks is required for efficient execution on this architecture. We propose Phoenix, a runtime system designed specifically for execution on CMP architectures to address the challenges of performance and programmability for upcoming HPC systems. An implementation of message passing interface (MPI) atop Phoenix is presented. Micro-benchmarks and a production MPI application are used to highlight the benefits of our implementation vis-a-vis traditional MPI implementations on CMP architectures.

/pdf/phoenix-a-runtime-environment-for-high-performance-computing-5374foycyh.pdf

Phoenix: A Runtime Environment for High Performance Computing on Chip Multiprocessors

Multi-core architectures provide the means to efficiently handle more fine-grained and larger numbers of parallel tasks. However, software still does not take advantage of these new possibilities, retaining the high cost associated with managing large numbers of threads. Batches of Threads have been introduced to reduce this cost and allow applications to express their inherent parallelism in a more fine-grained manner. In this paper, their use is extended, in order to improve two significant aspects of threading run-time systems. Firstly, to schedule large numbers of threads to processors. Secondly, to recycle data structures of threads that have finished execution. Both improvements can be implemented internally in threading run-time systems and thus are transparent to the programmer. The experimental evaluation demonstrates that basic thread operations improve significantly.

Improving basic thread operations with batches of threads

We used the Spin model checker to show that Intel's implementation of software transactional memory is correct, and built a preprocessor to accelerate the performance of Spin on parameterized models of shared-memory protocols.

/pdf/model-checking-transactional-memory-with-spin-4t1h0v1fc4.pdf

Model checking transactional memory with spin

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Runtime Environment for Terascale Platforms