This paper presents the 8th BCD generation integrating power and high voltage devices in a 0.18 μm technology node platform. Both dense 1.8 V and 3.3 V logic CMOS are available to realize complex monolithic solutions in the field of smart power applications.

BCD8 from 7V to 70V: a new 0.l8μm Technology Platform to Address the Evolution of Applications towards Smart Power ICs with High Logic Contents

This paper presents a novel technique and system for increasing the efficiency of dc-dc converters that supply dynamic electronic loads, such as modern audio and video equipment and other devices whose power consumption largely depends on the digital data they process. The optimization does not require a current-measurement circuit and is well-suited to portable applications. It is based on a real-time prediction of the dc-dc converter output current from easily accessible digital data streams present in the targeted loads. The result of the prediction is used for dynamic adjustment of the power-stage transistor size and/or for switching into pulse-frequency-mode of output voltage regulation, in order to maximize the instantaneous converter efficiency on-the-fly. The use of a segmented power-stage allows the effective power-transistor size to be changed on-the-fly, and the tradeoff between the gate-drive and rms conduction losses is continuously optimized over the full range of operation. The effectiveness of the optimization is demonstrated on an experimental system, including a 1-W digitally controlled 4-MHz, 3.6 V-1.8 V buck converter with an integrated segmented power-stage and a digital high-fidelity class-D audio amplifier acting as the digital load. The results show a good agreement between the digitally predicted and actual dc-dc converter load current, as well as a reduction in total energy consumption of up to 38%.

Predictive Efficiency Optimization for DC–DC Converters With Highly Dynamic Digital Loads

Toshiba's 5th generation BiCD/CD-0.13 is a new process platform for analog power applications based on 0.13µm CMOS technology. The process platform has six varieties of rated voltage, 5V, 6V, 18V, 25V, 40V, and 60V. 5 to 18V CD-0.13 process use P-type silicon substrate. 25 to 60V BiCD-0.13 process use N-Epi wafer with N+/P+ buried layer on P type silicon substrate. Each LDMOS recode ultra-low on-resistance compared with that of previous papers, and we will realize the highest performance analog power IC's using this technology.

Ultra-low on-resistance LDMOS implementation in 0.13µm CD and BiCD process technologies for analog power IC's

For the first time, we report a novel L-shaped trench LDMOS on silicon-on-insulator with double (lateral and vertical) enhanced dielectric field (ENDIF) (DENDIF) effect. This device features an L-shaped trench for accumulating charges (mainly, ionized charges) to enhance lateral breakdown voltage (BV). Then, the vertical ENDIF can be self-adaptive to the lateral ENDIF due to the lumped charges (mainly, inversion charges) at the interface of the buried oxide/silicon. The L-shaped trench makes the potential contours as tree roots, which can spread into the folded drift region to prevent premature breakdown in silicon. The simulated results of the DENDIF LDMOS show that the electric field in the dielectric layer is >; 200 V/μm, the gate-drain charge density (Qgd) is 0.39 nC/mm2, and the Baliga's figure of merit [(FOM); FOM = BV2/RON,sp] is 11.9 MW/cm2.

An L-Shaped Trench SOI-LDMOS With Vertical and Lateral Dielectric Field Enhancement

We present a new BCD technology in a 0.18 μm technology platforms with a capability of 7 to 60V high-voltage devices such as DEMOS and LDMOS. The developed 0.18 mum BCD process provides various kinds of high voltage LDMOS such as 7, 12, 20, 50, 60 V LDMOS transistors for variety of applications. The power LDMOS transistors in the process have very competitive specific on-resistance compared to previous results.

BD180 - a new 0.18 μm BCD (Bipolar-CMOS-DMOS) Technology from 7V to 60V

The performance of low-to-medium voltage power devices (7V-30V) implemented in an advanced 0.25μm BiCMOS-DMOS process is presented. The devices were optimized for a range of applications in this voltage group. In particular the lateral dmos devices have a capability of operating with the drain fully isolated from the substrate. The Rsp - BVdss performance for these devices is shown to be very competitive with respect to similar technologies. This performance is achieved without sacrificing the requirements for square electrical and lifetime safe operating area (SOA).

7 to 30V state-of-art power device implementation in 0.25 μm LBC7 BiCMOS-DMOS process technology

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7 to 30V state-of-art power device implementation in 0.25 μm LBC7 BiCMOS-DMOS process technology