A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.

Method for Fabricating Semiconductor Device

This invention includes methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation, and methods of forming bit line over capacitor arrays of memory cells. In one implementation, a semiconductor substrate having an exposed outer first surface comprising silicon-nitrogen bonds and an exposed outer second surface comprising at least one of silicon and silicon dioxide is provided. A layer comprising a metal is deposited over at least the outer second surface. A silanol is flowed to the metal of the outer second surface and to the outer first surface effective to selectively deposit a silicon dioxide comprising layer over the outer second surface as compared to the outer first surface. Other aspects and implementations are contemplated.

Methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation, and methods of forming arrays of memory cells

A complementary metal-oxide semiconductor (CMOS) image sensor and a method for fabricating the same are disclosed. The image sensor includes a sub-layer having a photodiode and a plurality of transistors formed thereon, a pad insulating layer formed on the sub-layer, a micro-lens formed on the pad insulating layer, the micro-lens including a first insulating layer having an uneven surface and a second insulating layer covering upper and side surfaces of a projected portion of the first insulating layer to form a dome shape, and a planarization layer formed on the micro-lens, and a color filter formed on the planarization layer.

CMOS image sensor and method for fabricating the same

A process for pre-tapering features in a material, such as silicon, prior to etching shallow trenches in the material includes opening a hard mask over the material such that first pre-tapered features are formed in the material. The process can include a hard mask overetch step, which modifies the profile of the first pre-tapered features to form second pre-tapered features in the material. Shallow trench isolation features are formed in the pre-tapered material.

Processes for pre-tapering silicon or silicon-germanium prior to etching shallow trenches

In accordance with an aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A silanol layer is formed to partially fill the trench and then converted, at least some of the silanol, to a compound including at least one of SiOn and RSiOn, where R includes an organic group. An electrically insulative material is formed over the converted silanol to fill the trench. In another aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A first layer of at least one of Si(OH)x and (CH3)ySi(OH)4-y is formed to partially fill the trench. At least some of the Si(OH)x if present is converted to SiO2 and at least some of (CH3)ySi(OH)4-y if present is converted to (CH3)xSiO2-x. Next, a layer of an electrically insulative material is formed to fill the trench.

Method of forming trench isolation regions

A method for forming insulator filled, shallow trench isolation regions, with rounded corners, has been developed. The process features the use of a polymer coated opening, in an insulator layer, used as a mask to define the shallow trench region in silicon. After completion of the shallow trench formation the polymer spacers are removed, exposing a region of unetched semiconductor, that had been protected by the polymer spacers, during the shallow trench dry etching procedure. The sharp corner, at the intersection between the shallow trench and the unetched region of semiconductor, is then converted to a rounded corner, via thermal oxidation of exposed silicon surfaces. The polymer spacers also eliminate the top corner wraparound.

Use of polymer spacers for the fabrication of shallow trench isolation regions with rounded top corners

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Use of polymer spacers for the fabrication of shallow trench isolation regions with rounded top corners