A variable capacitor is provided. The variable capacitor includes a plurality of capacitor segments. The plurality of capacitor segments are connected in parallel within the variable capacitor. When a plurality of candidate capacitances allowable to the variable capacitor according to a connection state of the plurality of capacitor segments connected in parallel are sorted in a magnitude sequence, the plurality of candidate capacitances form a geometric series. The variable capacitor is used for a Voltage Controlled Oscillator (VCO), and the VCO is used for a Phase Locked Loop (PLL).

Voltage controlled oscillator using variable capacitor and phase locked loop using the same

A variable leaf capacitor is disclosed. In accordance with some embodiments of the present disclosure, a variable leaf capacitor may comprise a first alternating current coupling capacitor having a first terminal coupled to a first differential node and a second terminal coupled to a first common-mode node, a second alternating current coupling capacitor having a first terminal coupled to a second differential node and a second terminal coupled to a second common-mode node, and a varactor having a bias terminal, a first common-mode terminal coupled to the first common-mode node, and a second common-mode terminal coupled to the second common-mode node, wherein the capacitance of the varactor is based on the voltage from the first common-mode terminal of the varactor to the bias terminal of the varactor and on the voltage from the second common-mode terminal of the varactor to the bias terminal of the varactor.

Frequency tuning and step control of a digitally controlled oscillator

A clock regeneration method, for generating a clock signal for being utilized by a receiver/transceiver/receiver system/transceiver system, includes: performing data/pattern detection on at least one input signal to generate recovered data; detecting at least one synchronization pattern in the input signal according to a synchronization pattern rule, and generating a synchronization signal corresponding to the synchronization pattern; and performing frequency-locking on the synchronization signal to generate the clock signal. More particularly, the step of detecting the at least one synchronization pattern in the input signal according to the synchronization pattern rule further comprises: detecting the at least one synchronization pattern by performing synchronization pattern detection on the recovered data. An associated reference-less receiver and an associated crystal-less system are also provided.

Clock regeneration method, reference-less receiver, and crystal-less system

PROBLEM TO BE SOLVED: To improve monotonicity and/or linearity in an analog-to-digital converter.SOLUTION: The system comprises an array of comparators each for converting analog input into digital output, a switch formed to adjust output bits of the digital output, and a control logic part. The control logic part initializes the switch and initializes a DC source providing the analog input. The control logic part is formed to increase the DC source for the unit of an advancing stride of a minimum voltage value corresponding to a least significant bit of the digital output. The control logic part is also formed to cause the switch to adjust one or more output bits of the digital output at least partially based on a value of the output bit corresponding to a present advancing stride.

Control system, control method and storage medium

A technique to provide hybrid compensation to correct for drifts in a reference frequency output from a digitally-controlled crystal oscillator (DCXO). A first compensation is provided to the DCXO to adjust for overlap or discontinuity of the reference frequency caused by switching capacitors in the capacitor array that controls drift of the reference frequency output. The second compensation is obtained at a phase-locked loop (PLL) that receives the reference frequency signal from the DCXO. The second compensation adjusts the PLL to adjust for variations of the reference frequency that remain after performing compensation in the DCXO.

Hybrid AFC using DCXO and RF PLL

Techniques for calibrating digitally controlled oscillators (DCOS) are disclosed In one aspect of the disclosure, an initial set of control codes for operating the DCO with a coarse frequency tuning bank with multiple overlapping coarse frequency tuning segments (LTBs) and one fine main frequency tuning bank (MTB) is determined A range of output frequencies produced from the initial set is identified Instances of overlap are identified in the frequency range between consecutive LTB segments An offset in the MTB is added that corresponds to the overlap instance between consecutive LTBs to establish a revised set The revised control codes are utilized to tune the DCO over the desired frequency range

Digitally controlled oscillator with improved digital frequency calibration

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Digitally controlled oscillator with improved digital frequency calibration