This paper reviews the evolution of the charge pumping (CP) technique and its applications from the micrometer-scale to the atomic-scale device era. We describe the more significant milestones of the CP technique (CPT) over the past couple of decades, giving insight into its potentialities. We start with the most popular one “traditional or conventional CP” and follow up with its different extensions in various fields like transistor reliability and radiation damage characterizations in devices fabricated with old and new semiconductor and dielectric materials. We show its easy adaptability for transistors with specific geometries. Advantages, weaknesses, as well as future tendencies of CPT and its variants, are also discussed.

Odyssey of the charge pumping technique and its applications from micrometric- to atomic-scale era

Effect of NC pins ESD test on the reliability of integrated circuits with high density BGA package

Revisiting row hammer: A deep dive into understanding and resolving the issue

RowPress Vulnerability in Modern DRAM Chips

In this work, we investigated the RowPress (RP) effect at the device-level for sub-20 nm DRAM. Utilizing 3D TCAD simulations, single-and double-sided RP are studied and compared with row hammer (RH) results. The distinct leakage mechanisms of RP are identified, illuminating its different cell vulnerability in contrast to RH. AWL-induced RP results in “0” failure, whereas PWL-induced RP leads to “1” failure, demonstrating different bit-flip directionality from RH. Furthermore, differences in the dependences on temperature and access pattern between RH and RP are highlighted, and the underlying mechanisms are analyzed.

Understanding the Physical Mechanism of RowPress at the Device-Level in Sub-20 nm DRAM

Short-term Negative Bias Temperature Instability (NBTI) was investigated in sub-20-nm DRAM technology. By using Variable <inline-formula> <tex-math notation="LaTeX">$\text{T}_{\text {charge}}$ </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">$\text{T}_{\text {discharge}}$ </tex-math></inline-formula> Amplitude Charge Pumping measurement, ultra-fast traps can be characterized with high accuracy. Both electron traps and hole traps are identified in the transistor. The energy and spatial distribution for these two traps can be clearly extracted. By further comparing with ab-initio calculation, the electron traps are found to relate to dangling bonds and hole traps originate from oxygen vacancies. Electron traps can contribute up to 90% in short-term NBTI and thus could be critical for future improvement. The results are useful in understanding the reliability of sub-20nm DRAM technology.

On the Understanding of Defects in Short-Term Negative Bias Temperature Instability (NBTI) for Sub-20-nm DRAM Technology

The degradation of HBM level caused by stressing no connect (NC) pins has been observed. The failed pins follow a statistical regularity whose distribution are adjacent to the NC pins. Two mechanisms, capacitance coupling and air arc, are discussed in details about the fail. Supplement model for the coupling and the C BB , capacitance between NC and signal ball, is introduced. Furthermore, Transmission Line Pulse (TLP) is used to characterize the transient behaviors during the fail and the arc between NC and failed pins, when the stress voltage reached to ~1.5 KV. By analyzing the degradation mechanisms, several ways are discussed to overcome this issue.

Improved Model for ESD Failure Caused by Stressing No Connect Pin

This work investigates the ON-state degradation under arbitrary stress conditions for periphery pFETs fabricated in the sub-20-nm DRAM technology. Three types of traps are identified, including the interface states, the oxide hole traps, and the oxide electron traps. By analyzing the time dependence, stress dependence, and lateral position, the generation mechanism for each type of trap is revealed, based on which a defect-based model was established. We proposed an effective model parameter extraction strategy and, thus, avoided overfitting. The predictive capability of the proposed model is further verified across the full bias regions at lower voltage conditions, including operating conditions. Finally, based on the model, the contributions of different types of traps to the degradation can be derived throughout the device’s entire lifetime. The work paves ways to link the defects to the device’s long-term reliability, which can be helpful for future process optimization and device/circuit co-optimization in DRAM peripheral circuits.

Defect-Based Empirical Model for On-State Degradation in Sub-20-nm DRAM Periphery pFETs Under Arbitrary Condition

An improved area-efficient transient ESD power clamp is proposed. It uses the double feedback circuit techniques to reduce the RC time constant, which saves the layout area. The new power clamp can discharge the ESD current and tolerate very fast power supply ramp rates and exhibit reduced area and leakage.

An Improved Area-efficient Transient ESD Power Clamp

Dielectric relaxation in high-κ storage capacitors can lead to significant degradation of capacitance values and hence deteriorate read bit-error rates of DRAMs. However, the mechanism of the dielectric relaxation phenomenon in high-κ dielectric oxides and multilayer stacks is still controversial. Moreover, previous work studied the dielectric relaxation phenomenon only at high-κ film level, which lacks the necessary insights into DRAM-specific complexities and performance improvement strategies. In this work, we first set up modeling and electric testing methodologies that can reliably collect and model dielectric relaxation signal in modern DRAM high-κ capacitors at both single-cell and chip levels. Experiment and simulation evidences based on these methodologies were then presented to identify and validate charge trapping-detrapping as the physical origin of dielectric relaxation in the frequency realm of DRAM operations. Dielectric relaxation performance improvement strategies were further provided, in particular for the latest storage capacitors with HfO2 being implemented.

Dielectric Relaxation Performance of DRAM Storage Capacitors and Ways of Improvement

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

Blacksmith Wu

Author Tools

Chat about Author