Bich-Yen Nguyen
Soitec
284 Papers
5.2K Citations
Bich-Yen Nguyen is an academic researcher from Soitec. The author has contributed to research in topics: Layer (electronics) & Gate dielectric. The author has an hindex of 47, co-authored 273 publications. Previous affiliations of Bich-Yen Nguyen include Motorola & Freescale Semiconductor.
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Papers
Patent
Method for forming pitch independent contacts and a semiconductor device having the same
Kent J. Cooper,Jung-Hui Lin,Scott S. Roth,Bernard J. Roman,Carlos A. Mazure,Bich-Yen Nguyen,Wayne J. Ray +6 more
- 03 Jun 1991
TL;DR: In this article, the etch stop material is removed from the contact region to expose a portion of the insulating layer, which is then anisotropic etched and at least one contact (30 and/or 32) is formed.
113
CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET)
Leo Mathew,Yang Du,Aaron Thean,Michael A. Sadd,A. Vandooren,Colita Parker,Tab A. Stephens,Rode R. Mora,R. Rai,M. Zavala,D. Sing,S. Kalpat,J. Hughes,Rob Shimer,S. Jallepalli,G.O. Workman,W. Zhang,Jerry G. Fossum,Bruce E. White,Bich-Yen Nguyen,J. Mogab +20 more
- 04 Oct 2004
TL;DR: In this article, perfectly self aligned vertical multiple independent gate field effect transistor (MIGFET) CMOS devices have been fabricated for mixed-signal applications and used as signal mixer.
111
A process/physics-based compact model for nonclassical CMOS device and circuit design
Jerry G. Fossum,L. Ge,Meng-Hsueh Chiang,V.P. Trivedi,M.M. Chowdhury,Leo Mathew,G. O. Workman,Bich-Yen Nguyen +7 more
TL;DR: In this article, a process/physics-based compact model (UFDG) for nonclassical MOSFETs having ultra-thin Si bodies (UTB) is overviewed.
110
Patent
Method of forming a vertical double gate semiconductor device and structure thereof
Leo Mathew,Bich-Yen Nguyen,Michael A. Sadd,Bruce E. White +3 more
- 31 Jan 2003
TL;DR: In this paper, a vertical double gate semiconductor device with separate, non-contiguous gate electrode regions is described, and contacts are formed over the separate gate electrodes regions that may or may not be electrically isolated from each other.
106
High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET
Kangguo Cheng,Ali Khakifirooz,Nicolas Loubet,Scott Luning,Toshiharu Nagumo,Maud Vinet,Qing Liu,Alexander Reznicek,Thomas N. Adam,Sebastian Naczas,Pouya Hashemi,J. Kuss,James Chingwei Li,H. He,Lisa F. Edge,J. Gimbert,Prasanna Khare,Yu Zhu,Z. Zhu,Anita Madan,N. Klymko,S. Holmes,T. Levin,Alex Hubbard,R. Johnson,M. Terrizzi,Sean Teehan,A. Upham,G. Pfeiffer,T. Wu,A. Inada,Frederic Allibert,Bich-Yen Nguyen,L. Grenouillet,Y. Le Tiec,Romain Wacquez,Walter Kleemeier,R. Sampson,Robert H. Dennard,Tak H. Ning,Mukesh Khare,Ghavam G. Shahidi,Bruce B. Doris +42 more
- 01 Dec 2012
TL;DR: A novel “STI-last” integration scheme is developed to improve cSiGe uniformity and enable ultra high performance PFET with narrow widths and modulates device Vt, thus providing an additional knob to enable multi-Vt while maintaining undoped channels for all devices.
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