The properties of pristine, free-standing graphene monolayers prepared by mechanical exfoliation of graphite are investigated. The graphene monolayers, suspended over open trenches, are examined by means of spatially resolved Raman spectroscopy of the G-, D-, and 2D-phonon modes. The G-mode phonons exhibit reduced energies (1580 cm-1) and increased widths (14 cm-1) compared to the response of graphene monolayers supported on the SiO2 covered substrate. From analysis of the G-mode Raman spectra, we deduce that the free-standing graphene monolayers are essentially undoped, with an upper bound of 2x10^11 cm-2 for the residual carrier concentration. On the supported regions, significantly higher and spatially inhomogeneous doping is observed. The free-standing graphene monolayers show little local disorder, based on the very weak Raman D-mode response. The two-phonon 2D mode of the free-standing graphene monolayers is downshifted in frequency compared to that of the supported region of the samples and exhibits a narrowed, positively skewed line shape.

Probing the Intrinsic Properties of Exfoliated Graphene: Raman Spectroscopy of Free-Standing Monolayers

Broadband convolutional processing using band-alignment-tunable heterostructures

GaN technology is not only gaining traction in power and RF electronics but is also rapidly expanding into other application areas including digital and quantum computing electronics. This paper provides a glimpse of future GaN device technologies and advanced modeling approaches that can push the boundaries of these applications in terms of performance and reliability. While GaN power devices have recently been commercialized in the 15–900 V classes, new GaN devices are greatly desirable to explore both higher-voltage and ultra-low-voltage power applications. Moving into the RF domain, ultra-high frequency GaN devices are being used to implement digitized power amplifier circuits, and further advances using the hardware–software co-design approach can be expected. On the horizon is the GaN CMOS technology, a key missing piece to realize the full-GaN platform with integrated digital, power, and RF electronics technologies. Although currently a challenge, high-performance p-type GaN technology will be crucial to realize high-performance GaN CMOS circuits. Due to its excellent transport characteristics and ability to generate free carriers via polarization doping, GaN is expected to be an important technology for ultra-low temperature and quantum computing electronics. Finally, given the increasing cost of hardware prototyping of new devices and circuits, the use of high-fidelity device models and data-driven modeling approaches for technology-circuit co-design are projected to be the trends of the future. In this regard, physically inspired, mathematically robust, less computationally taxing, and predictive modeling approaches are indispensable. With all these and future efforts, we envision GaN to become the next Si for electronics.

Emerging GaN technologies for power, RF, digital, and quantum computing applications: Recent advances and prospects

Two-dimensional crystals have emerged as a class of materials that may impact future electronic technologies. Experimentally identifying and characterizing new functional two-dimensional materials is challenging, but also potentially rewarding. Here, we fabricate field-effect transistors based on few-layer black phosphorus crystals with thickness down to a few nanometres. Reliable transistor performance is achieved at room temperature in samples thinner than 7.5 nm, with drain current modulation on the order of 10(5) and well-developed current saturation in the I-V characteristics. The charge-carrier mobility is found to be thickness-dependent, with the highest values up to ∼ 1,000 cm(2) V(-1) s(-1) obtained for a thickness of ∼ 10 nm. Our results demonstrate the potential of black phosphorus thin crystals as a new two-dimensional material for applications in nanoelectronic devices.

http://absimage.aps.org/image/MAR14/MWS_MAR14-2013-005031.pdf

Black Phosphorus Field-effect Transistors

With the increasing demand for multispectral information acquisition, infrared multispectral imaging technology that is inexpensive and can be miniaturized and integrated into other devices has received extensive attention. However, the widespread usage of such photodetectors is still limited by the high cost of epitaxial semiconductors and complex cryogenic cooling systems. Here, we demonstrate a noncooled two-color infrared photodetector that can provide temporal-spatial coexisting spectral blackbody detection at both near-infrared and mid-infrared wavelengths. This photodetector consists of vertically stacked back-to-back diode structures. The two-color signals can be effectively separated to achieve ultralow crosstalk of ~0.05% by controlling the built-in electric field depending on the intermediate layer, which acts as an electron-collecting layer and hole-blocking barrier. The impressive performance of the two-color photodetector is verified by the specific detectivity (D*) of 6.4 × 109 cm Hz1/2 W-1 at 3.5 μm and room temperature, as well as the promising NIR/MWIR two-color infrared imaging and absolute temperature detection. 

/pdf/van-der-waals-two-color-infrared-photodetector-2weoj9w2.pdf

Van der Waals two-color infrared photodetector

Semiconductor devices that rely on quantum tunnelling could be of use in logic, memory and radiofrequency applications. Tunnel devices that exhibit negative differential resistance typically follow an operating principle in which the tunnelling current contributes directly to the drive current. Here, we report a tunnelling field-effect transistor made from a black phosphorus/Al2O3/black phosphorus van der Waals heterostructure in which the tunnelling current is in the transverse direction with respect to the drive current. Through an electrostatic effect, this tunnelling current can induce a drastic change in the output current, leading to a tunable negative differential resistance with a peak-to-valley ratio of more than 100 at room temperature. Our device also exhibits abrupt switching, with a body factor (the relative change in gate voltage with respect to that of the surface potential) that is one-tenth of the Boltzmann limit for conventional transistors across a wide temperature range. A black phosphorus/Al2O3/black phosphorus heterostructure can be used to create a tunnel field-effect transistor in which the tunnelling current is in the transverse direction with respect to the drive current, leading to abrupt switching and a negative differential resistance with a peak-to-valley ratio of more than 100 at room temperature.

A transverse tunnelling field-effect transistor made from a van der Waals heterostructure

Enhancement-mode (E-mode) GaN MOS-HEMTs using recess process typically face the challenge of precise thickness control, surface roughness issue, and interface traps, all of which could lead to the degradation of the device performance and cause reliability issues. In this article, we use a combined process of atomic layer etching (ALE) technique and atomic layer deposited (ALD) HfSiO dielectric. ALE is repeated oxidation and dry etching process with minimal surface damage, leading to a precisely controlled low-damage recess channel area. The fabricated AlGaN/GaN MOS-HEMTs exhibit E-mode operation with a positive threshold voltage ( ${V}_{\text {th}}$ ) of +2.1 V with small ${V}_{\text {th}}$ dispersion for different devices, an ultrahigh drain current ON– OFF ratio over 1010 and a low ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) of $11.5~\Omega \cdot \text {mm}$ at gate-to-drain length ( ${L}_{\text {GD}}$ ) of $25~\mu \text{m}$ . Source field plate (SFP) structure is employed to reduce the charge trapping process and improve the reliability at high voltages. The current collapse of the E-mode device with SFP structure can be effectively suppressed due to the optimized redistribution of the peak electric field in the gate-to-drain access region, where a significantly improved dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of only 1.17 times increase from the static ${R}_{ \mathrm{\scriptscriptstyle ON}}$ after OFF-state ${V}_{\text {DS}}$ stress of 600 V. Moreover, the enhanced vertical electric field with decreased AlGaN barrier thickness and the positive shift in threshold voltage for the E-mode device can effectively suppress the current collapse, which outperforms the depletion-mode counterpart. The breakdown voltage reaches a considerable value of 1560 V at an OFF-state current density of ${1}~\mu \text{A}$ /mm.

Improved Current Collapse in Recessed AlGaN/GaN MOS-HEMTs by Interface and Structure Engineering

DOI: 10.1002/aelm.201800711 electrical performance from individual or few devices and wafer-scale uniformity analysis is still lacking. Up to now, a few reported complex graphene RF circuits utilized several graphene devices with similar electrical properties. For instance, Han et al. reported a graphene RF receiver integrated circuit consisting of three graphene RF devices.[7] Lyu et al. also demonstrated a double-balanced graphene gate-pumped resistive mixer integrated circuit and a graphene distributed amplifier, both of which included four graphene RF devices.[8,9] It is noted that it is necessary for RF circuits to use multistage amplifier circuits in a cascade structure to obtain high gain. Thus the uniform electrical performance of each sublevel stage is critical to obtain stable impedance matching networks which are placed at the input network, in-between stages, and output network. In light of this, it would be desirable to fabricate a large number of graphene RF devices with excellent electrical performance, high uniformity, and acceptable yield across the whole wafer. In the meantime, large-area graphene growth and transfer are also essential for practical and commercial applications. Recently, the development of large-scale and high-quality single crystalline graphene films grown by chemical vapor deposition (CVD) method has provided the basis for batch fabrication of high-performance wafer-scale graphene devices.[10,11] Previous studies have successfully demonstrated the viable way of wafer-scale fabrication process of graphene RF devices including CVD graphene and SiC epitaxial graphene.[6,8,12–20] Although some progress has been made in the basic direct current (DC) characteristics on a wafer scale, none of the reports show wafer-scale analysis of the RF characteristics.[18,21,22] In this work, we have systematically studied the overall uniformity of the CVD graphene not only on material characterization, but also comprehensive DC and RF electrical characterization including spatial distribution mapping of Raman spectrum, Dirac voltage VDirac, maximum transconductance gm,max, fT*Lg, fmax/fT, small signal open-circuit voltage gain Z21/Z11, and forward power gain |S21| of graphene transistors throughout the entire 4-inch HfSiO/Si wafer. Large-area graphene film was grown by CVD using the copper pocket method Radio frequency (RF) transistor based on graphene has attracted tremendous research efforts in the past few years. Despite the fact that such material is developed on a wafer-scale level, the majority of reported high performance of individual transistors is limited to individual or a few devices. As a result, the electronic uniformity and stability study on a large number of transistors remain unexplored especially for RF performance, which are the most critical factors for any practical applications. In this work, a comprehensive statistical analysis of the uniformity of DC and RF characteristics simultaneously for hundreds of transistors fabricated from transferred largearea CVD-grown graphene in a 4-inch HfSiO/Si wafer is carried out for the first time. For devices with the same gate length of 0.8 μm, the coefficient of variation (CV) for Dirac point voltage and extrinsic peak transconductance is only 0.07 and 0.03, respectively. In addition, the intrinsic fT*Lg is high up to about 20 GHz · μm, which is among the best value for the graphene RF transistors. More importantly, the CV for the as-measured fmax/fT is as low as 0.11, indicating highly uniform RF characteristics across the 4-inch wafer. Transistors

Wafer Scale Mapping and Statistical Analysis of Radio Frequency Characteristics in Highly Uniform CVD Graphene Transistors

Failure Mechanisms Investigation of Ultra-Thin Composite Polymer Electrolyte-Based Solid-State Lithium Batteries

The invention discloses a silicon carbide junction barrier schottky diode and a preparation method thereof. The silicon carbide junction barrier schottky diode comprises a cathode electrode, a siliconcarbide substrate, a first drift layer and a second drift layer which are arranged in turn from the bottom to the top and first field limiting rings, second field limiting rings, a passivation layerand an anode electrode. The depth of the first field limiting rings is less than that of the first drift layer and the first field limiting rings are distributed in the first drift layer in a spaced way and leveled with the upper surface of the first drift layer. The width of the second field limiting rings is less than that of the first field limiting rings and the depth is the same as that of the second drift layer and the second field limiting rings are distributed in the second drift layer in a spaced way. The first field limiting rings and the second field limiting rings are identical innumber and correspondingly in the inverted T-shape or n L-shape distribution. The anode electrode is located on the main junction, and the passivation layer is located on both sides of the anode electrode. The breakdown voltage of the schottky diode is increased and the difficulty of the preparation process is reduced.

Silicon carbide junction barrier schottky diode and preparation method thereof

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