Design automation for embedded systems comprising both hardware and software components demands for code generators integrated into electronic CAD systems. These code generators provide the necessary link between software synthesis tools in HW/SW codesign systems and embedded processors. General-purpose compilers for standard processors are often insufficient, because they do not provide flexibility with respect to different target processors and also suffer from inferior code quality. While recent research on code generation for embedded processors has primarily focussed on code quality issues, in this contribution we emphasize the importance of retargetability, and we describe an approach to achieve retargetability. We propose usage of uniform, external target processor models in code generation, which describe embedded processors by means of RT-level netlists. Such structural models incorporate more hardware details than purely behavioral models, thereby permitting a close link to hardware design tools and fast adaptation to different target processors. The MSSQ compiler, which is part of the MIMOLA hardware design system, operates on structural models. We describe input formats, central data structures, and code generation techniques in MSSQ. The compiler has been successfully retargeted to a number of real-life processors, which proves feasibility of our approach with respect to retargetability. We discuss capabilities and limitations of MSSQ, and identify possible areas of improvement.

Retargetable Code Generation Based on Structural Processor Description

Foreword. Preface. 1. Introduction. 2. Processor Modelling. 3. Instruction-Set Extraction. 4. Code Generation. 5. Instruction-Level Parallelism. 6. The Record Compiler. 7. Conclusions. References. Index.

Retargetable Code Generation for Digital Signal Processors

Efficient design of embedded processors plays a critical role in embedded systems design. Processor description languages and their associated specification, exploration and rapid prototyping methodologies are used to find the best possible design for a given set of applications under various design constraints, such as area, power and performance. 

This book is the first, comprehensive survey of modern architecture description languages and will be an invaluable reference for embedded system architects, designers, developers, and validation engineers. Readers will see that the use of particular architecture description languages will lead to productivity gains in designing particular (application-specific) types of embedded processors.

* Comprehensive coverage of all modern architecture description languages... use the right ADL to design your processor to fit your application;
* Most up-to-date information available about each architecture description language from the developers...save time chasing down reliable documentation;
* Describes how each architecture desccription language enables key design automation tasks, such as simulation, synthesis and testing...fit the ADL to your design cycle;

Processor Description Languages

Due to the need for fast design cycles and low production cost, programmable targets like DSP processors are becoming increasingly popular. Design planning, detailed design as well as updating such designs requires mapping existing algorithms onto these targets. Instead of writing target-specific mappers, we propose using retargetable mappers. The technique reported in this paper is based on pattern matching. Binary code is generated as a result of this matching process. This paper describes the techniques of our mapper MSSV and identifies areas for improvements. As a result, it shows that efficient handling of alternative mappings is crucial for an acceptable performance.

Tree-based mapping of algorithms to predefined structures

A machine-independent high-level microprogramming language, called MPGL, has been developed along with its processing system, called MPG. The MPGL allows the microprogrammer to write microprograms sequentially in a machine-independent fashion. The MPG provides the facility for translating these microprograms into efficient object code, as well as debugging object microprograms.

The MPG System: A Machine-Independent Efficient Microprogram Generator

We propose a design methodology based on data flow analysis for a functionally distributed, multiprocessor database machine. We define a cost model of database processing with the objective cost being response time of a set of query strategies. Heuristic optimization techniques are proposed using the operations of grouping, decomposition, and replication. We apply the new optimization techniques in several realistic multiprocessor environments. The resulting configurations of multiprocessors demonstrate significant performance improvements over more traditional designs.

Design of a Functionally Distributed, Multiprocessor Database Machine Using Data Flow Analysis

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The MPG System: A Machine-Independent Efficient Microprogram Generator

Design of a Functionally Distributed, Multiprocessor Database Machine Using Data Flow Analysis