B. Yang
Advanced Micro Devices
8 Papers
103 Citations
B. Yang is an academic researcher from Advanced Micro Devices. The author has contributed to research in topics: PMOS logic & CMOS. The author has an hindex of 6, co-authored 8 publications.
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Papers
•Proceedings Article
High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm 2 SRAM and ultra low-k back end with eleven levels of copper
Brian J. Greene,Q. Liang,K. Amarnath,Y. Wang,J. Schaeffer,M. Cai,Yue Liang,S. Saroop,J. Cheng,A. Rotondaro,Shu-Jen Han,R. Mo,K. McStay,S.H. Ku,R. Pal,Mahender Kumar,B. Dirahoui,B. Yang,F. Tamweber,Woo-Hyeong Lee,M. Steigerwalt,H. Weijtmans,Judson R. Holt,L. Black,S. Samavedam,M. Turner,K. Ramani,D. Lee,Michael P. Belyansky,M. Chowdhury,D. Aime,B. Min,H. van Meer,Haizhou Yin,K.K. Chan,M. Angyal,M. Zaleski,O. Ogunsola,C. Child,L. Zhuang,H. Yan,D. Permanaa,Jeffrey W. Sleight,Dechao Guo,S. Mittl,D. Ioannou,Ernest Y. Wu,Michael P. Chudzik,D.-G. Park,D. Brown,Scott Luning,Dan Mocuta,Edward P. Maciejewski,K. Henson,Effendi Leobandung +54 more
- 01 Jun 2006
TL;DR: In this paper, a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 µm2 is presented, enabling performance without the power penalty from gate capacitance.
61
On implementation of embedded phosphorus-doped SiC stressors in SOI nMOSFETs
Zhibin Ren,G. Pei,James Chingwei Li,Bin Yang,R. Takalkar,K.K. Chan,Guangrui Xia,Z. Zhu,Anita Madan,Teresa L. Pinto,Tijjani Adam,J. Miller,Abhishek Dube,L. Black,J.W. Weijtmans,B. Yang,Eric C. Harley,A. Chakravarti,Thomas S. Kanarsky,R. Pal,Isaac Lauer,Dae-Gyu Park,D. K. Sadana +22 more
- 17 Jun 2008
TL;DR: In this paper, the authors report a successful implementation of epitaxially grown Phosphorus-doped (Pdoped) embedded SiC stressors into SOI nMOSFETs and identify a process integration scheme that best preserves the SiC strain and minimizes parasitic resistance.
14
Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current
B. Yang,K. Nummy,Andrew Waite,L. Black,H. Gossmann,H. Yin,Y. Liu,B. Kim,S. Narasimha,Philip A. Fisher,H.V. Meer,J. Johnson,D. Chidambarrao,S. D. Kim,C. D. Sheraw,D. Wehella-gamage,Judson R. Holt,X. Chen,Donggun Park,C.Y. Sung,D. Schepis,M. Khare,Scott Luning,P. Agnello +23 more
- 12 Jun 2007
TL;DR: In this article, the authors demonstrate that the mobility advantage of (110) PMOS over 100 PMOS is maintained down to 190 nm liners poly-pitch for devices under compressive stress.
13
(110) channel, SiON gate-dielectric PMOS with record high I on =1 mA/μm through channel stress and source drain external resistance (R ext ) engineering
B. Yang,Andrew Waite,Haizhou Yin,Jian Yu,L. Black,Dureseti Chidambarrao,Anthony G. Domenicucci,X. Wang,S.H. Ku,Y. Wang,H.V. Meer,Byeong Y. Kim,Hasan M. Nayfeh,Seong-Dong Kim,Keith H. Tabakman,R. Pal,K. Nummy,Brian J. Greene,Philip A. Fisher,Jinping Liu,Q. Liang,Judson R. Holt,Shreesh Narasimha,Z. Luo,Henry K. Utomo,X. Chen,D.-G. Park,Chun-Yung Sung,Richard A. Wachnik,Gregory G. Freeman,Dominic J. Schepis,Edward P. Maciejewski,Mukesh Khare,Effendi Leobandung,Scott Luning,Paul D. Agnello +35 more
- 01 Dec 2007
TL;DR: In this article, the authors present for the first time (110) PMOS characteristics without Rext degradation, allowing investigation of fundamental mobility and demonstration of drive current Ion in excess of 1mA/mum at Ioff =100 nA/μm.
10
Recent Progress and Challenges in Enabling Embedded Si:C Technology
B. Yang,Zhibin Ren,R. Takalkar,Linda Black,Abhishek Dube,Johan W. Weijtmans,John Li,Ka Kong Chan,J. P. de Souza,Anita Madan,Guangrui Xia,Z. Zhu,J. Faltermeier,Alexander Reznicek,Thomas N. Adam,Ashima B. Chakravarti,G. Pei,Rohit Pal,Bin Yang,Eric C. Harley,Brian J. Greene,A. Gehring,M. Cai,D. K. Sadana,D.-G. Park,Dan Mocuta,Dominic J. Schepis,Edward P. Maciejewski,Scott Luning,E. Leobandung +29 more
- 29 Aug 2008
TL;DR: This work demonstrates that integrating ISPD eSi:C stressor in the thick-oxide long-channel nMOS source and drain is feasible and key challenges lie in both high-quality ISPD EPI development and modification of the conventional Si CMOS fabrication process to preserve eSi-C strain.
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