Transparent flexible fluorine-doped indium zinc oxide (IZO:F) thin-film transistors (TFTs) were demonstrated using the spin-coating method of the metal fluoride precursor aqueous solution with annealing at 200°C for 2 hrs on polyethylene naphthalate films The proposed thermal evolution mechanism of metal fluoride aqueous precursor solution examined by thermogravimetric analysis and Raman spectroscopy can easily explain oxide formation The chemical composition analysed by XPS confirms that the fluorine was doped in the thin films annealed below 250°C In the IZO:F thin films, a doped fluorine atom substitutes for an oxygen atom generating a free electron or occupies an oxygen vacancy site eliminating an electron trap site These dual roles of the doped fluorine can enhance the mobility and improve the gate bias stability of the TFTs Therefore, the transparent flexible IZO:F TFT shows a high mobility of up to 41 cm2/V·s and stable characteristics under the various gate bias and temperature stresses

/pdf/solution-processed-flexible-fluorine-doped-indium-zinc-oxide-39o54ixsqm.pdf

Solution-Processed Flexible Fluorine-doped Indium Zinc Oxide Thin-Film Transistors Fabricated on Plastic Film at Low Temperature

Current status and challenges of aggressive equivalent-oxide-thickness (EOT) scaling of high-κ gate dielectrics via higher-κ ( > 20) materials and interfacial layer (IL) scavenging techniques are reviewed. La-based higher-κ materials show aggressive EOT scaling (0.5-0.8 nm), but with effective workfunction (EWF) values suitable only for n-type field-effect-transistor (FET). Further exploration for p-type FET-compatible higher-κ materials is needed. Meanwhile, IL scavenging is a promising approach to extend Hf-based high-κ dielectrics to future nodes. Remote IL scavenging techniques enable EOT scaling below 0.5 nm. Mobility-EOT trends in the literature suggest that short-channel performance improvement is attainable with aggressive EOT scaling via IL scavenging or La-silicate formation. However, extreme IL scaling (e.g., zero-IL) is accompanied by loss of EWF control and with severe penalty in reliability. Therefore, highly precise IL thickness control in an ultra-thin IL regime ( < 0.5 nm) will be the key technology to satisfy both performance and reliability requirements for future CMOS devices.

Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging?

High-k dielectrics have been intensively investigated during the last decade, and their performance as a gate dielectric has been improved to the level of conventional SiO2-based gate dielectric at an equivalent oxide thickness (EOT) ~1 nm. The understanding on metal electrodes and their interaction with the underlying high-k dielectric has been expanded, and various CMOS device results with metal electrode/high-k gate dielectric stacks have been reported, indicating the maturity of this technology. The next challenges lie in scaling the gate stack to 0.5-nm EOT to extend the usage of the metal electrode/high-k gate dielectric stacks to future technology generations. A new class of high-k dielectric that has a dielectric constant higher than 26 and a barrier height of ~5.0 eV and above will be needed to achieve this target. Recent progress in this so-called higher k dielectric research is summarized, and its benefit to the gate leakage current is discussed. This paper also reviews various extrinsic and intrinsic process-related defects in the deep subnanometer gate stacks and the potential challenges in implementing such a gate-stack system.

Metal Electrode/High- $k$ Dielectric Gate-Stack Technology for Power Management

High-k/germanium (Ge) interfaces are significantly improved through a new interface engineering scheme of using both effective pregate surface GeO2 passivation and postgate dielectric (postgate) treatment incorporating fluorine (F) into a high-k/Ge gate stack. Capacitance-voltage (C-V) characteristics are significantly improved with minimum density of interface states (Dit) of 2 times 1011 cm-2 ldr eV-1 for Ge MOS capacitors. A hole mobility up to 396 cm2/V ldr s is achieved for Ge p-metal-oxide-semiconductor field-effect transistors (pMOSFETs) with equivalent oxide thickness that is ~10 Aring and gate leakage current density that is less than 10-3 A/cm2 at Vt plusmn 1 V. A high drain current of 37.8 muA/mum at Vg - Vt = Vd = -1.2 V is presented for a channel length of 10 mum. The Ge MOSFET interface properties are further investigated using the variable-rise-and-fall-time charge-pumping method. Over three times Dit reduction in both upper and lower halves of the Ge bandgap is observed with F incorporation, which is consistent with the observation that frequency-dependent flat voltage shift is much less for samples with F incorporation in the C-V characteristics of Ge MOS capacitors.

Interface-Engineered High-Mobility High- $k$ /Ge pMOSFETs With 1-nm Equivalent Oxide Thickness

Using a fluorinated high-fc/metal gate stack combined with a stress relieved preoxide (SRPO) pretreatment before high-fc deposition, we show significant device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem, and performance degradation for high-fc is a concern. The novel fluorinated TaxCy/HfZrOx/SRPO gate stack device exceeds the positive-bias-temperature-instability and negative-bias-temperature-instability targets with sufficient margin and has electron mobility at 1 MV/cm comparable to the industrial high-quality polySi/SiON device on bulk silicon.

Defect Passivation With Fluorine and Interface Engineering for Hf-Based High- $k$ /Metal Gate Stack Device Reliability and Performance Enhancement

Using a novel fluorinated TaxCy/high-k gate stack, we show breakthrough device reliability and performance improvements This is a critical result since threshold voltage instability may be a fundamental problem and performance degradation for high-k is a concern The novel fluorinated gate stack device exceeds the PBTI and NBTI targets with sufficient margin and has electron mobility comparable to the best polySi/SiON device on bulk Si reported so far

Defect passivation with fluorine in a Ta/sub x/C/ high-K gate stack for enhanced device threshold voltage stability and performance

For the first time we report on the development of a novel hafnium zirconate (HfZrOx) gate dielectric with a TaxCy metal gate Compared to HfO2, the new HfZrOx gate dielectric showed: (1) higher transconductance, (2) less charge trapping, (3) higher drive current, (4) lower NMOS Vt, (5) reduced C-V hysteresis, (6) lower interface state density, (7) superior wafer-level thickness uniformity, and (8) longer PBTI lifetime We attribute these improvements to a microstructure that is modified by addition of Zr to HfO2

Microstructure modified HfO/sub 2/ using Zr addition with Ta/sub x/ C/sub y/ gate for improved device performance and reliability

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Defect passivation with fluorine in a Ta/sub x/C/ high-K gate stack for enhanced device threshold voltage stability and performance

Microstructure modified HfO/sub 2/ using Zr addition with Ta/sub x/ C/sub y/ gate for improved device performance and reliability