B. Smith
Motorola
12 Papers
525 Citations
B. Smith is an academic researcher from Motorola. The author has contributed to research in topics: CMOS & Process window. The author has an hindex of 4, co-authored 12 publications.
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Papers
Patent
Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
Veena Misra,Suresh Venkatesan,Christopher C. Hobbs,B. Smith,Jeffrey S. Cope,Earnest B. Wilson +5 more
- 11 Aug 1997
Abstract: A method for forming a metal gate MOS transistor begins by forming source and drain electrodes (26, 28, and/or 118) within a substrate (12 or 102). These source and drain regions (26, 28, and 118) are self-aligned to a lithographically-patterned feature (24 or 108). After formation of the source and drain regions, the features (24 and 108 are processed to fill these features with a metallic gate layer (28a or 128a). This metal layer (28a or 128a) is then chemically mechanically polished (CMPed) to form a metallic plug region (28b or 128b) within the features (24 or 108). The plug region (28b or 128b) is formed in either an inlaid or dual inlaid manner wherein this metallic plug region (28b or 128b) is self-aligned to the previously formed source and drain regions and preferably functions as a metal MOS gate region.
236
A high performance 1.8 V, 0.20 /spl mu/m CMOS technology with copper metallization
Suresh Venkatesan,A.V. Gelatos,B. Smith,R. Islam,J. Cope,B. Wilson,D. Tuttle,R. Cardwell,S. Anderson,M. Angyal,R. Bajaj,C. Capasso,P. Crabtree,Saroj Das,J. Farkas,Stanley M. Filipiak,B. Fiordalice,Melissa Freeman,Percy V. Gilbert,M. Herrick,Ajay Jain,H. Kawasaki,Charles Fredrick King,Jeffrey L. Klein,T. Lii,Kimberly G. Reid,T. Saaranen,Cindy Reidsema Simpson,T. Sparks,Paul G. Y. Tsui,R. Venkatraman,David K. Watts,E.J. Weitzman,R. Woodruff,I. Yang,Navakanta Bhat,Gregory Norman Hamilton,Y. Yu +37 more
- 07 Dec 1997
TL;DR: In this paper, a high performance 020 /spl mu/m logic technology has been developed with six levels of planarized copper interconnects, optimized for 18 V operation to provide high performance with low power-delay products and excellent reliability.
191
Proximity dummy feature placement and selective via sizing for process uniformity in a trench-first-via-last dual-inlaid metal process
Ruiqi Tian,R. Boone,S. Chheda,B. Smith,Xiaoping Tang,Edward O. Travis,D.F. Wong +6 more
- 06 Jun 2001
TL;DR: In this article, the authors modeled resist thickness at a via location as a weighted sum of nearby trench densities, layout modifications of proximity dummy feature placement and selective via sizing are introduced to increase via size uniformity.
70
A high performance 3.97 /spl mu/m/sup 2/ CMOS SRAM technology using self-aligned local interconnect and copper interconnect metallization
M. Woo,Mousumi Bhat,M. Craig,P. Kenkare,X. Wnag,F. Tolic,H. Chuang,Sanjay Parihar,J. Schmidt,L. Terpolilli,R. Pena,D. Derr,N. Cave,P. Crabtree,M. Capetillo,S. Filipiak,T. Lii,A. Nagy,D. O'Meara,T. Vuong,M. Blackwell,R. Larson,M. Wilson,James D. Hayden,S. Venkatesan,Paul G. Y. Tsui,Percy V. Gilbert,A. Perera,Chitra K. Subramanian,T. McNelly,Veena Misra,R. Islam,B. Smith,J. Farkas,David K. Watts,Dean J. Denning,Sam S. Garcia,Larry E. Frisa,S. Iyer,Craig S. Lage +39 more
- 09 Jun 1998
TL;DR: In this paper, a 3.97 /spl mu/m/sup 2/6T CMOS bitcell technology has been developed using a logic based platform incorporating a self-aligned local interconnect and copper metallization.
21
A comparison of via overetch variations between conventional Al-W and dual-inlaid copper integrations
B. Smith,S. Blackley,Russell L. Carter,S. Chheda,P. Crabtree,D. Farber,Martin Gall,R. Islam,D. Jawarani,Charles Fredrick King,D. Menke,R. Nelson,L. Pressley,David Smith,T. Sparks,Tab A. Stephens,Edward O. Travis,Suresh Venkatesan +17 more
- 24 May 1999
TL;DR: In this article, a comparison of via overetch is made between a conventional integration using aluminum interconnects plus tungsten via plugs and a dual-inlaid integration using copper.
4