Graphics processors require strong arithmetic support to perform computational kernels over data streams. Because of the current implementation using the basic arithmetic operations, the algorithms are given in algebraic terms. However, since the operations are really of a geometric nature, it seems to us that more flexibility in the implementation is obtained if the description is given in a high-level geometrical form. As a consequence of this line of thought, this paper is an attempt to reconsider some kernels in a graphics processor to obtain implementations that are potentially more scalable than just replicating the modules used in conventional implementations. We present the formulation of representative 3D computer graphics operations in terms of CORDIC-type primitives. Then, we briefly outline a stream processor based on CORDIC-type modules to efficiently implement these graphic operations. We perform a rough comparison with current implementations and conclude that the CORDIC-based alternative might be attractive.

High-throughput CORDIC-based geometry operations for 3D computer graphics

Numerically controlled oscillators (NCOs), with a hybrid scheme of both look-up tables (LUT) and coordinate transformation digital computer (CORDIC) algorithms for a hardware efficient, high performance sine/cosine function generation are investigated. This scheme combines fast access and power efficiency of reasonably sized LUTs, and arbitrary precision obtainable from a rigorous iteration algorithm. Systematic studies using hardware description language (HDL) models and synthesis lead to optimum LUT/CORDIC ratios, which minimize power consumption and silicon area for a given operating clock frequency. First order error models are presented as guidelines for choosing internal NCO parameters. The NCO accuracy is tested with HDL simulations for all algorithmic states to limit output errors to 1 least significant bit (LSB) and by spectra derived from discrete Fourier transform (DFT) for typical frequency inputs f, resulting in a signal to noise ratio (SNR) of better than 100 dB for an amplitude word length AW of 16 bit. Two benchmark designs were adopted for the two clock frequencies 200 MHz and 20 MHz, as "high" and "moderate" performance, respectively. The NCO models are synthesized in a 0.35 /spl mu/m CMOS standard cell target technology and optimized to actually achieve after layout maximum clock frequencies exceeding 310 MHz, i.e., signal frequencies of up to 100 MHz.

Numerically controlled oscillators with hybrid function generators

We propose a modified fast algorithm for discrete cosine transform (DCT) by transferring the results from the discrete Hartley transform (DHT) to one additional CORDIC (coordinate rotation digital computer) computing stage. A fast CORDIC-based systolic array is designed with four derived attractive features, including: (1) the single/double data folding feature; (2) the constructive feature; (3) the to-computing feature; and (4) the redundant computation. Due to its properties, the proposed design has an efficient hardware utilization and a high throughput rate. By using the redundant path, this design also has the capability of error detection. >

High throughput CORDIC-based systolic array design for the discrete cosine transform

This paper describes the application of high radix redundant CORDIC algorithms to complex logarithmic number system arithmetic. It shows that a CLNS addition can be performed with approximately the same hardware as a high-radix CORDIC operation. A design example comparable to single precision floating point has been designed and simulated.

/pdf/complex-logarithmic-number-system-arithmetic-using-high-2a5psx9p0c.pdf

Complex logarithmic number system arithmetic using high-radix redundant CORDIC algorithms

Design methodologies for high performance Direct Digital Fre-quen--cy Synthesizers (DDFS) are described. Traditional look-up tab-les (LUT) for sine and co-sine are merged with CORDIC-inter-po---la--tion into a hybrid architecture. This implements DDFS-sys-tems with high resolution without being specific to a particular tar-get technology. Amplitude constants were obtained from ma-the-matical trigonometric functions of the IEEE math_real pack-age. These constants were then written via simulation of a VHDL model into a fully synthesizable package. Systematic and detailed studies varying the synthesizers inherent parameters lead to a design optimum of the LUT/CORDIC-ra-tio, which mini-mizes power and silicon area for a given clock frequency.

VHDL-based design and design methodology for reusable high performance direct digital frequency synthesizers

This work describes a floating-point arithmetic unit based on the CORDIC algorithm. The unit computes a full set of high level arithmetic and elementary functions: multiplication, division, (co)sine, hyperbolic (co)sine, square root, natural logarithm, inverse (hyperbolic) tangent, vector norm, and phase. The chip has been integrated in 1.6 /spl mu/m double-metal n-well CMOS technology and achieves a normalized peak performance of 220 MFLOPS. >

A CMOS floating-point vector-arithmetic unit

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A CMOS floating-point vector-arithmetic unit