Ayan Datta
IBM
9 Papers
54 Citations
Ayan Datta is an academic researcher from IBM. The author has contributed to research in topics: Logic gate & Chip. The author has an hindex of 3, co-authored 9 publications. Previous affiliations of Ayan Datta include Intel.
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Papers
Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module
James D. Warnock,Yuen Chan,Hubert Harrer,S. Carey,Gerard M. Salem,Doug Malone,Ruchir Puri,Jeffrey A. Zitz,Adam R. Jatkowski,Gerald Strevig,Ayan Datta,Anne E. Gattiker,Aditya Bansal,Guenter Mayer,Yiu-Hing Chan,M. Mayo,David L. Rude,L. Sigal,Thomas Strach,Howard H. Smith,Huajun Wen,Pak-Kin Mak,C-L Kevin Shum,Donald W. Plass,Charles F. Webb +24 more
TL;DR: Various aspects of the design are explored in detail, with most of the focus on the CP chip, including the circuit design implementation, clocking, thermal modeling, reliability, frequency tuning, and comparison to the previous design in 45nm technology.
28
5.5GHz system z microprocessor and multi-chip module
James D. Warnock,Y.-H. Chan,Hubert Harrer,David L. Rude,Ruchir Puri,S. Carey,Gerard M. Salem,Guenter Mayer,Yiu-Hing Chan,M. Mayo,Adam R. Jatkowski,Gerald Strevig,L. Sigal,Ayan Datta,Anne E. Gattiker,Aditya Bansal,D. Malone,Thomas Strach,Huajun Wen,Pak-Kin Mak,Chung-Lung Shum,Donald W. Plass,Charles F. Webb +22 more
- 28 Mar 2013
TL;DR: The new System z microprocessor chip (“CP chip”) features a high-frequency processor core running at 5.5GHz in a 32nm high-κ CMOS technology, a successor to the 45nm product, with significant improvements made to the core and nest.
24
Patent
Programmable integrated circuit standard cell
Ayan Datta,Ankur Shukla,James D. Warnock +2 more
- 26 Sep 2016
TL;DR: In this paper, a standard cell for use within an integrated circuit can be partially personalized by local wiring, where the set of transistors can be connected to a set of local nodes by local wires.
5
Patent
Programmable delay circuit including hybrid fin field effect transistors (finFETs)
Vijay K. Ankenapalli,Ayan Datta,Sumitha George,Charudhattan Nagarajan,James D. Warnock +4 more
- 08 Jul 2015
TL;DR: In this paper, a first stage comprising a first hybrid fin field effect transistor (finFET) comprising of a first control FET, and a second gate corresponding to a first default FET and a plurality of fins, where the first gate and the second gate of the first stage each partially control a first shared fin of the second plurality of fin.
2
Design-synthesis co-optimisation using skewed and tapered gates
Ayan Datta,James D. Warnock,Ankur Shukla,Saurabh Gupta,Yiu. H. Chan,Karthik Mohan,Charudhattan Nagarajan +6 more
- 14 Mar 2016
TL;DR: A novel technique to optimize the design of non-conventional tapered and skewed standard cell gates, and the synthesis algorithms for efficient usage of such gates in IBMs high-performance 22nm CMOS SOI technology is presented.
2