This paper presents the first linear bulk CMOS power amplifier (PA) targeting low-power fifth-generation (5G) mobile user equipment integrated phased array transceivers. The output stage of the PA is first optimized for power-added efficiency (PAE) at a desired error vector magnitude (EVM) and range given a challenging 5G uplink use case scenario. Then, inductive source degeneration in the optimized output stage is shown to enable its embedding into a two-stage transformer-coupled PA; by broadening interstage impedance matching bandwidth and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured $P_{\text {out}}$ /PAE at −25 dBc EVM for a 250 MHz-wide 64-quadrature amplitude modulation orthogonal frequency division multiplexing signal with 9.6 dB peak-to-average power ratio. The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6 dB back-off from saturation. To the best of the authors’ knowledge, these are the highest measured PAE values among published ${K}$ - and Ka -band CMOS PAs.

A Highly Efficient and Linear Power Amplifier for 28-GHz 5G Phased Array Radios in 28-nm CMOS

This article reviews the state-of-the-art millimeter-wave (mm-wave) power amplifiers (PAs), focusing on broadband design techniques. An overview of the main solid-state technologies is provided, including Si, gallium arsenide (GaAs), GaN, and other III–V materials, and both field-effect and bipolar transistors. The most popular broadband design techniques are introduced, before critically comparing through the most relevant design examples found in the scientific literature. Given the wide breadth of applications that are foreseen to exploit the mm-wave spectrum, this contribution will represent a valuable guide for designers who need a single reference before adventuring in the challenging task of the mm-wave PA design.

/pdf/a-review-of-technologies-and-design-techniques-of-millimeter-wekhp9uz17.pdf

A Review of Technologies and Design Techniques of Millimeter-Wave Power Amplifiers

To meet rising demand, broadband-cellular-data providers are racing to deploy fifth generation (5G) mm-wave technology, e.g., rollout of some 28GHz-band services is intended in 2017 in the USA with ∼5/1Gb/s downlink/uplink targets. Even with 64-QAM signaling, this translates to an RF bandwidth (RFBW) as large as ∼800MHz. With ∼100m cells and a dense network of 5G access points (APs), potential manufacturing volumes make low-cost CMOS technology attractive for both user equipment (UE) and AP devices. However, the poor P out and linearity of CMOS power amplifiers (PAs) are a bottleneck, as ∼10dB back-off is typical for meeting error-vector-magnitude (EVM) specifications. This limits communication range and PA power added efficiency (PAE), with wider RFBWs accentuating these issues further. On the other hand, sufficient element counts in the envisaged 5G phased-array modules can overcome path loss despite low P out per PA, e.g., by combining RFICs in an AP. CMOS PAs with wideband linearity/PAE can therefore enable economical UE/AP devices to deliver 5G data-rates.

2.7 A wideband 28GHz power amplifier supporting 8×100MHz carrier aggregation for 5G in 40nm CMOS

Rapidly growing demand for broadband-cellular-data traffic is driving fifth-generation (5G) wireless standardization towards the deployment of gigabit-per-second mm-Wave technology by 2020. Paving the road to 5G, 200m coverage in non-line-of-sight (NLOS) urban cells was demonstrated using practical antenna arrays at 28GHz [1], and the FCC recently issued a notice of inquiry into the provision of mobile services above 24GHz. Battery life and thermal limitations make power efficiency critical in the envisioned user-equipment (UE) phased-array transceivers, particularly for power amplifiers (PAs), which operate at 8-to-10dB power back-off (PBO) to transmit broadband, high-peak-to-average power-ratio (PAPR) signals with high fidelity. Higher yields and lower costs for integrated phased arrays make CMOS the preferred choice over other more-power-efficient technologies, e.g. GaAs. Furthermore, calibrating an integrated array of PAs, e.g. by using digital pre-distortion, is prohibitively complex for high-volume manufacturing. Thus, maximizing PAE of inherently linear CMOS PA circuits at PBO is a major challenge for future 5G UE radios.

20.6 A 28GHz efficient linear power amplifier for 5G phased arrays in 28nm bulk CMOS

The race on the Complementary Metal-Oxide-Semiconductor (CMOS) More Moore integration scale has brought to light several major limitations for efficient planar process integration starting with the 40 nm technology node. The transistor channel was more and more difficult to control in terms of electrostatics, and many process engineering methods (such as, for example, Silicon strain) were used to provide transistors with good carrier speed and decent electrical characteristics. Starting from the 28-nm node, the obvious solution for transistors with increased electrical performances was the use of fully depleted devices. Two integration methods have been identified by the semiconductor industry for these fully depleted devices: Fully Depleted Silicon on Insulator (FD-SOI) CMOS and Fin-FET CMOS devices. While the fundamental carrier semiconductor equations are similar, the process integration is very different. This article focuses on planar FDSOI CMOS technology features as integrated by STMicroelectronics in the 28-nm node [1], [2], and its specificities for analog, radio frequency (RF), millimeter wave (mmW), and mixed signal systemon-chip (SoC) integration.

Fully Depleted Silicon on Insulator Devices CMOS: The 28-nm Node Is the Perfect Technology for Analog, RF, mmW, and Mixed-Signal System-on-Chip Integration

The widespread deployment of high-data-rate wireless connectivity was enabled by the adoption of the WiGig (802.11ad) standard, consequently placing a challenge on integrated Power Amplifiers (PAs). To comply with system requirements, the PA must cover bands from 57 to 66GHz and deliver up to 10dBm RF modulated power, while OFDM modulations up to 16 or 64QAM are supported, implying a large Peak-to-Average Power Ratio (PAPR).

2.10 A 60GHz 28nm UTBB FD-SOI CMOS reconfigurable power amplifier with 21% PAE, 18.2dBm P 1dB and 74mW P DC

A 60 GHz highly linear Power Amplifier (PA) is implemented in 65-nm Low Power (LP) CMOS technology. The structure consists of four common-source pseudo-differential stages. To improve global performances, a compact transformer-based 8-way power combiner is designed. Three driver stages are neutralized with capacitors to enhance both reverse isolation and power gain. At 60 GHz, the PA delivers a saturated output power (PSAT) of 19.9 dBm and a 1-dB compressed output power (P-1dB) of 17.2 dBm while achieving maximum power added efficiency (PAEmax) of 20 %. The small-signal gain is about 33 dB with a 3-dB bandwidth of 9 GHz. The circuit occupies an active area of 0.32 mm2. To the author's knowledge, this amplifier presents the highest figure of merit (FOM ITRS) among 60 GHz PAs using silicon technology.

A 1.2V 20 dBm 60 GHz power amplifier with 32.4 dB Gain and 20 % Peak PAE in 65nm CMOS

An amplifier includes at least two amplification stages coupled in parallel. Each amplification stage includes at differential pair of amplifying MOS transistors having gates connected to a first and second input nodes common to amplifying stages, and bulk regions connected to each other but insulated from bulk regions of the amplifying MOS transistors of the other amplification stages. A configuration circuit generates bias voltage for application to the bulk terminals in each amplification stage to set the threshold voltages of the amplifying MOS transistors, and thus configuring the operating range of each amplification stage so that different amplification stages have different operating ranges.

Multiple range rf amplifier

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2.10 A 60GHz 28nm UTBB FD-SOI CMOS reconfigurable power amplifier with 21% PAE, 18.2dBm P 1dB and 74mW P DC

A 1.2V 20 dBm 60 GHz power amplifier with 32.4 dB Gain and 20 % Peak PAE in 65nm CMOS

Multiple range rf amplifier