The author points out the importance of the involvement of the design and manufacturing team in achieving reliability of microelectronic devices. A method of verifying reliability goals through calculation of failure rates based on life test parameters is described. An example illustrating the method is shown. >

Microelectronics reliability

Increasing the capacity of the Last Level Cache (LLC) can help scale the memory wall. Due to prohibitive area and leakage power, however, growing conventional SRAM LLC already incurs diminishing returns. Emerging Non-Volatile Memory (NVM) technologies like Spin Torque Transfer RAM (STTRAM) promise high density and low leakage, thereby offering an attractive alternative for building large capacity LLCs. However these technologies have significantly longer write latency compared to SRAM, which interferes with reads and severely limits their performance potential. Despite the recent work showing the write latency reduction at NVM technology level, practical considerations like high yield and low bit error rates will result a significant loss of NVM density when these techniques are implemented. Therefore, improving the write latency while compromising on the density results in sub-optimal usage of the NVM technology. In this paper we present a novel STTRAM LLC design that mitigates the long write latency, thereby delivering SRAM like performance while preserving the benefits of high density. Based on a light-weight learning mechanism, our solution relieves LLC congestion through two schemes. Firstly, we propose write congestion aware bypass that eliminates a large fraction of writes. Despite dropping LLC hit rates which could severely degrade performance in a conventional LLC, our policy smartly modulates the bypass, overcomes the hit rate loss and delivers significant performance gain. Furthermore, our solution establishes a virtual hybrid cache that absorbs and eliminates the redundant writes, which otherwise might be repeatedly and slowly written to the NVM LLC. Detailed simulation of traditional SPEC CPU 2006 suite as well as important industry workloads running on a 4-core system shows that our proposal delivers on an average 26% performance improvement over a baseline LLC design using 8MB STTRAM, while reducing the memory system energy by 10%. Our design outperforms a similar area SRAM LLC by nearly 18%, thereby making NVM technology an attractive alternative for future high performance computing.

Density tradeoffs of non-volatile memory as a replacement for SRAM based last level cache

The research and prototyping of new memory technologies are getting a lot of attention in order to enable new (computer) architectures and provide new opportunities for today's and future applications. Delivering high quality and reliability products was and will remain a crucial step in the introduction of new technologies. Therefore, appropriate fault modelling, test development and design for testability (DfT) is needed. This paper overviews and discusses the challenges and the emerging solutions in testing three classes of memories: 3D stacked memories, Resistive memories and Spin-Transfer-Torque Magnetic memories. Defects mechanisms, fault models, and emerging test solutions will be discussed.

/pdf/challenges-and-solutions-in-emerging-memory-testing-kjkb0iot61.pdf

Challenges and Solutions in Emerging Memory Testing

Spin transfer torque (STT) switching-based magnetic random access memory (MRAM) is gaining significant industrial and academic attention due to its potential application as a non-volatile memory device in computing devices, smartphones, and so on. STT-MRAM devices with in-plane magnetization configuration have been marketed as niche products. Devices with out-of-plane magnetization are being considered for embedded memory as the first step. Aggressive goals include replacing dynamic random access memory (DRAM) with STT-MRAM. This review article introduces the basics of STT-MRAM and describes the recent progress in overcoming certain challenges such as reduction of power consumption and increase of storage density, which will make it a strong competitor for DRAM.

Recent Developments in Spin Transfer Torque MRAM

Spin-transfer-torque magnetic RAM (STT-MRAM) is one of the most promising emerging memory technologies. As various manufacturing vendors make significant efforts to push it to the market, appropriate STT-MRAM testing is of great importance. In this paper, we demonstrate that conventional STT-MRAM defect modeling, which is based on linear resistors, is too pessimistic in representing the real nature of physical defects. It may result in incorrect fault models, which in turn can lead to low-quality test solutions. In addition, we propose a generic defect modeling methodology which captures the nonlinear behavior of STT-MRAM defects accurately; a defect is modeled by adjusting the affected STT-MRAM technology parameters. The methodology is illustrated by two examples, namely a pinhole defect and a sidewall redeposition defect, which are simulated for accurate fault modeling. In case of a pinhole defect, the STT-MRAM suffers from a fast transition between magnetic tunnel junction (MTJ) states with increased write current, making the MTJ more vulnerable to breakdown. However, with the conventional linear resistor as defect model the memory shows a slow transition or even a transition failure. Similarly, a sidewall redeposition defect causes a fast transition without current elevation, which is not observed when using the conventional approach.

Electrical Modeling of STT-MRAM Defects

Spin transfer torque magnetic random access memory (STT-MRAM) is a competitive, future memory technology for last-level embedded caches. It exhibits ultra-high density (3–4X of SRAM), non-volatility, nano-second Read and Write speeds, and process and voltage compatibility with CMOS. As the design and fabrication process mature for the STT-MRAM, there is a need to study the various fault models that can affect this novel memory technology. This work presents a comprehensive analysis of fault models which represent both parametric variations as well as defects (opens and shorts) in STT MRAM. Sensitivity of Read, Write and Retention to process (material and lithographic) parameters, defects (both intra-cell and inter-cell) and data patterns are studied.

Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is an emerging memory technology which exhibits non-volatility, high density, high endurance and nanosecond read and write times. These attributes of STT-MRAM make it suitable for last level embedded caches. However, defect models, faults and test architectures for emerging memory technologies are relatively unexplored. This is further aggravated by the fact that STT-MRAM, like other post-CMOS technologies rely on novel physics of operation, which can result in unexplored read, write and retention fault models. In particular, the stochastic retention failure of STT-MRAM has a large impact on the test time. Conventional test schemes for retention of STT-MRAM need to be redesigned and optimized for testing large STT-MRAM arrays. This paper presents a comprehensive analysis of read, write and retention tests in STT-MRAM arrays. Resistive and capacitive defects and the corresponding faults are studied. A novel MBIST architecture and associated circuits are presented for measuring thermal stability (and hence retention times) in STT-MRAM bits for characterization and manufacturing tests, amidst variations and magnetic coupling. Trade-offs between fault localization, area overhead and test-times are presented.

EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays

There has been a significant interest in Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) as a candidate for emerging memory technology for last-level embedded caches in the recent years. High density (3-4x of SRAM), non-volatility, nano-second Read and Write speeds, and process and voltage compatibility with CMOS are the attractive properties of this technology. A few studies have expounded on the reliability in this technology but various fault manifestations have not been studied in detail in the past. This paper attempts to study the fault models in STT-MRAM under both parametric variations as well as electrical defects (opens and shorts). Sensitivity of Read, Write and Retention to material and lithographic process parameters has been studied. Also electrical defects viz. intra-cell and inter-cell opens and shorts have been considered and the corresponding fault models have been identified and classified.

A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays

MATHS (Mechanism to Access Test-Data over High-Speed Link) provides a high-throughput PCIe based system to structurally test system-on-chips (SOCs) at wafer and system-level. The system removes the need for expensive test equipment by eliminating the input/output pin (IO) requirements and memory per IO needs. It simplifies the ATE architecture and design to enable smaller form factors and reduce capital costs of ownership. MATHS enables eliminating the assembly test-insertion by directly testing the SOCs on system level platforms, further reducing the costs. Since the mechanism is based on PCIe standards, it is highly portable across all platforms including ATE, system-level test, board, and in-field testing.

NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links

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Papers

Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays

EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays

A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays

NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links