This study aims to describe the errors of prospective teacher students in making math test instruments based on cognitive levels from the Bloom’s Taxonomy Revised (BTR). BTR consists of LOTS (C1-C3) and HOTS (C4-C6) levels. This research included descriptive qualitative research. The subjects of this study were 19 prospective teacher students, namely the mathematics education department in the Mathematics Learning Evaluation course. Based on the results of the study, it was obtained that prospective teacher students made mistakes at both levels but more at the HOTS level. At the LOTS level, it is on the error level C3; at the HOTS level, it is spread at all levels, namely C4-C6. An indication of error that often arises is that prospective teacher students cannot compile questions according to their level of cognition. The questions made are often still below the level they should be. The level of the questions made is still below the level that it should be.

Analysis of Prospective Teacher Students Errors in Making Math Test Instruments Based on Bloom's Taxonomy Revised

The Mechanism to Access Test-Data over High-Speed Link (MATHS) provides a high-throughput PCIe-based system to structurally test system-on-chips (SoCs) at wafer and system levels. With this system, the SoC can be directly tested at the system level and the reliance on expensive test equipment. Since MATHS simplifies the necessary ATE architecture and design, smaller and lower cost testers can be employed to test the SoC. The system is based on PCIe standards, making it highly portable across all platforms, including ATE, system-level test, board, and in-field testing.

NVIDIA MATHS: Mechanism to Access Test-Data Over High-Speed Links

MATHS (Mechanism to Access Test-Data over High-Speed Link) provides a high-throughput PCIe based system to structurally test system-on-chips (SOCs) at wafer and system-level. The system removes the need for expensive test equipment by eliminating the input/output pin (IO) requirements and memory per IO needs. It simplifies the ATE architecture and design to enable smaller form factors and reduce capital costs of ownership. MATHS enables eliminating the assembly test-insertion by directly testing the SOCs on system level platforms, further reducing the costs. Since the mechanism is based on PCIe standards, it is highly portable across all platforms including ATE, system-level test, board, and in-field testing.

NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links

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NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links