Ankit More
Intel
34 Papers
134 Citations
Ankit More is an academic researcher from Intel. The author has contributed to research in topics: Network on a chip & CMOS. The author has an hindex of 7, co-authored 34 publications. Previous affiliations of Ankit More include Drexel University.
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Papers
Synchrotrace: synchronization-aware architecture-agnostic traces for light-weight multicore simulation
Siddharth Nilakantan,Karthik Sangaiah,Ankit More,Giordano Salvadory,Baris Taskin,Mark Hempstead +5 more
- 29 Mar 2015
TL;DR: The SynchroTrace methodology is presented, a scalable, flexible, and accurate trace-based multi-threaded simulation methodology that captures synchronization- and dependency-aware, architecture-agnostic, multi- threaded traces and uses a replay mechanism that plays back these traces correctly.
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P 4 : Phase-based power/performance prediction of heterogeneous systems via neural networks
Yeseong Kim,Pietro Mercati,Ankit More,Emily Shriver,Tajana Rosing +4 more
- 13 Nov 2017
TL;DR: P4 is proposed, a new Phase-based Power and Performance Prediction framework which identifies cross-platform application power and performance at runtime for heterogeneous computing systems and builds neural network-based models to automatically identify and generalize the complex cross- Platform relationships for each benchmark phase.
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SynchroTrace: Synchronization-Aware Architecture-Agnostic Traces for Lightweight Multicore Simulation of CMP and HPC Workloads
Karthik Sangaiah,Michael Lui,Radhika Jagtap,Stephan Diestelhorst,Siddharth Nilakantan,Ankit More,Baris Taskin,Mark Hempstead +7 more
TL;DR: This work presents SynchroTrace, a scalable, flexible, and accurate trace-based multithreaded simulation methodology that is able to accurately model the nondeterminism of multith readed programs for different hardware platforms and threading paradigms.
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Simulation based study of on-chip antennas for a reconfigurable hybrid 3D wireless NoC
Ankit More,Baris Taskin +1 more
- 01 Sep 2010
TL;DR: It is shown that it is possible to have two different frequency domains for the signal sources and the dynamic switching of the signal sinks between the two frequency domains, with minimal design and area overhead.
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•Proceedings Article
Wireless interconnects for inter-tier communication on 3D ICs
Ankit More,Baris Taskin +1 more
- 01 Nov 2010
TL;DR: In this paper, the feasibility of on-chip antennas for inter-tier communication on a 3D integrated circuit (IC) stack is shown for two different 3D integration processes: oxide-oxide bonding and metal oxide semiconductor (CMOS) silicon on insulator (SoI) polymer adhesive bonding 3D circuit integration technology.
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