Alexandre Hubert
Commissariat à l'énergie atomique et aux énergies alternatives
13 Papers
59 Citations
Alexandre Hubert is an academic researcher from Commissariat à l'énergie atomique et aux énergies alternatives. The author has contributed to research in topics: Nanowire & Dynamic random-access memory. The author has an hindex of 5, co-authored 12 publications. Previous affiliations of Alexandre Hubert include Centre national de la recherche scientifique.
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Papers
Modeling stress retarded self-limiting oxidation of suspended silicon nanowires for the development of silicon nanowire-based nanodevices
Pier-Francesco Fazzini,Caroline Bonafos,Alain Claverie,Alexandre Hubert,Thomas Ernst,Marc Respaud +5 more
TL;DR: Hu et al. as discussed by the authors presented a model for the oxidation of silicon nanowires (NWs) based on a modification of the cylindrical Deal and Grove equation and taking into account stress effects associated with non-uniform deformation of the oxide by viscous flow.
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Experimental comparison of programming mechanisms in 1T-DRAM cells with variable channel length
Alexandre Hubert,Maryline Bawedin,Georges Guegan,Sorin Cristoloveanu,Thomas Ernst,Olivier Faynot +5 more
- 01 Nov 2010
TL;DR: In this paper, the impact of the gate length reduction on impact ionization and meta-stable dip (MSD) programming mechanisms was analyzed and it was found that MSD is less impacted by the scaling of standard SOI MOSFETs without specific optimization.
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Dimensional effects and scalability of Meta-Stable Dip (MSD) memory effect for 1T-DRAM SOI MOSFETs
TL;DR: In this paper, the effect of transistor dimensions on the MSD effect was investigated and the experimental results were discussed and validated by two-dimensional numerical simulations, showing that MSD is maintained for small dimensions even in standard SOI MOSFETs, although specific optimizations are expected to enhance MSDRAM performances.
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Oxidation of Suspended Stacked Silicon Nanowire for Sub-10nm Cross-Section Shape Optimization
Alexandre Hubert,Jean-Philippe Colonna,Stéphane Bécu,Cecilia Dupre,V. Maffini-Alvaro,Jean-Michel Hartmann,Sébastien Pauliac,C. Vizioz,F. Aussenac,Catherine Carabasse,Vincent Delaye,Thomas Ernst,Simon Deleonibus +12 more
- 24 Oct 2008
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Floating-Body SOI Memory: The Scaling Tournament
Maryline Bawedin,Maryline Bawedin,Sorin Cristoloveanu,Alexandre Hubert,K.-H. Park,Frédéric Martinez +5 more
- 01 Jan 2011
TL;DR: An overview of the typical device architectures of the single transistor capacitorless dynamic random access memory (1T-DRAM), which uses only one transistor and takes advantage of floating body effects in SOI and SOI-like devices.
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