We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.

Interpolation and SAT-based model checking

The efficient synthesis of quantum circuits is an active research area. Since many of the known quantum algorithms include a large Boolean component (e.g. the database in the Grover search algorithm), quantum circuits are commonly synthesized in a two-stage approach. First, the desired function is realized as a reversible circuit making use of existing synthesis methods for this domain. Afterwards, each reversible gate is mapped to a functionally equivalent quantum gate cascade. In this paper, we propose an improved mapping of reversible circuits to quantum circuits which exploits a certain structure of many reversible circuits. In fact, it can be observed that reversible circuits are often composed of similar gates which only differ in the position of their target lines. We introduce an extension of reversible gates which allow multiple target lines in a single gate. This enables a significantly cheaper mapping to quantum circuits. Experiments show that considering multiple target lines leads to improvements of up to 85% in the resulting quantum cost.

/pdf/improving-the-mapping-of-reversible-circuits-to-quantum-khh2m3zeo4.pdf

Improving the mapping of reversible circuits to quantum circuits using multiple target lines

Reversible circuits, i.e. circuits which map each possible input vector to a unique output vector, build the basis for emerging applications e.g. in the domain of low-power design or quantum computation. As a result, researchers developed various approaches for synthesis of this kind of logic. In this paper, we consider the ESOP-based synthesis method. Here, functions given as Exclusive Sum of Products (ESOPs) are realized. In contrast to conventional circuit optimization, the quality of the resulting circuits depends thereby not only on the number of product terms, but on further criteria as well. In this paper, we present an approach based on an evolutionary algorithm which optimizes the function description with respect to these criteria. Instead of ESOPs, Pseudo Kronecker Expression (PSDKRO) are thereby utilized enabling minimization within reasonable time bounds. Experimental results confirm that the proposed approach enables the realization of circuits with significantly less cost.

/pdf/improving-esop-based-synthesis-of-reversible-logic-using-10iig9gg9a.pdf

Improving ESOP-based synthesis of reversible logic using evolutionary algorithms

The development of approaches for synthesis and optimization of reversible circuits received significant attention in the past. This is partly due to the increasing emphasis on low power design methodologies, and partly motivated by recent works in quantum computation. While most of them relied on a gate library composed of multiple-control Toffoli (MCT) gates with positive control lines, some initial works also exist which additionally incorporate negative control lines. This usually leads to smaller circuits with respect to the number of gates as well as the corresponding quantum costs. However, despite these benefits, negative control lines have hardly been considered in post-synthesis optimization of reversible circuits so far. In this paper, we address this issue. We are presenting an optimization scheme inspired by template matching which explicitly makes use of negative control lines. Experimental evaluations demonstrate that exploiting negative control lines in fact lead to a reduction in the number of gates and the quantum costs by up to 60% and 25%, respectively.

/pdf/exploiting-negative-control-lines-in-the-optimization-of-4400j3q2tr.pdf

Exploiting negative control lines in the optimization of reversible circuits

Since the selection of the Rijndael cryptosystem as a new Advanced Encryption Standard (AES) in 2000, many hardware implementations of AES have been reported. Some of these implementations are optimized for speed, some for area, some for reconfigurability, and some for low-power applications. Again, reversible logic synthesis methodologies have drawn the attention of researchers in recent times, mainly with the prospect of quantum computing becoming a reality, and the potential of reversible logic circuits for providing ultra low-power implementations. Although many of the cryptographic primitives are inherently reversible by nature, very little work has been done towards reversible logic implementations of the same. The only published works relate to reversible implementations of Montgomery multiplication algorithm, which has applications in cryptography. The present paper, possibly for the first time, presents a reversible logic implementation of a block cipher, namely, 128-bit AES. The various AES functional blocks have been synthesized using reversible gates, using which an overall reversible architecture has been proposed. The pipelined version as suggested can only be used in the Electronic Code Book (ECB) mode. The hardware complexity of the implementation has been evaluated using the number of reversible gates required and the quantum cost.

Reversible logic implementation of AES algorithm

We present FoREnSiC, an open source environment for automatic error detection, localization and correction in C programs. The framework implements different automated debugging methods in a unified way covering the whole design flow from ESL to RTL. Currently, a scalable simulation-based back-end, a back-end based on symbolic execution, and a formal back-end exploiting functional equivalences between a C program and a hardware design are available. FoREnSiC is designed as an extensible framework. Its infrastructure, including a powerful front-end and interfaces to logic problem solvers, can be reused for implementing new program analysis or debugging methods. In addition to the infrastructure, the back-ends, and a few experimental results, we present an illustrative application scenario that shows FoREnSiC in use.

/pdf/forensic-an-automatic-debugging-environment-for-c-programs-4k5t2ryd4c.pdf

FoREnSiC: an automatic debugging environment for C programs

FoREnSiC - An Automatic Debugging Environment for C Programs

Verifying correctness is a major bottleneck in today's circuit and system design. Verification includes the tasks of error detection, error localization, and error correction in an implemented design, as well as the analysis and avoidance of transient faults. For all those tasks, knowing when an assignment to signals becomes observable at the outputs and for how long it influences the system is important. In this letter, we propose a minimal and maximal latency measure for sequential circuits. This measure explains how long a circuit's state and outputs depend on input stimuli. Exact and heuristic algorithms are discussed to determine the measure. We evaluate the algorithms on state-of-the-art designs. Experimental results show how the measure provides insight into the behavior of circuit designs.

/pdf/latency-analysis-for-sequential-circuits-1qa02evq0a.pdf

Latency Analysis for Sequential Circuits

Due to the increasing complexity modern System on Chip designs are developed by large design teams. In addition, existing design blocks are re-used such that the knowledge about these parts of the design entirely depends on the quality of the documentation. For a single designer it is almost impossible to have detailed knowledge about all blocks and their interaction. We introduce a simulation-based automation technique to support design understanding. Based on use cases provided by the designer and on their coverage information, the proposed technique identifies parts of the source code that are relevant for a certain functional feature. In two case studies the technique is shown to be at least as exact as reading the documentation with two important advantages: the automated approach is fast and more precise than the existing documentation for the inspected designs.

/pdf/automated-feature-localization-for-hardware-designs-using-221dntu13u.pdf

Automated feature localization for hardware designs using coverage metrics

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