Abstract A design of a broadband Doherty power amplifier (DPA) using a novel harmonic control network (HCN) is presented. The DPA structure focused on manipulating harmonic components using this new HCN to enhance the bandwidth of operation and power efficiency. The proposed HCN combines a third harmonic suppression network (THSN) with the second harmonic impedance inverter circuit (SHIIC). In the design, the second harmonic component of the main transistor and the peaking transistor are short‐circuited by their associated SHIIC. Additionally, the carefully designed SHIIC and THSN circuit placed between the main and peaking transistors realise open circuit conditions at the third harmonic for both transistors at the saturation state and back‐off regions. Side by side with the aid of the properly designed post‐matching tuned network (PMTN), these harmonic loading conditions make both amplifiers to operate in continuous Class‐F modes with enhanced‐added efficiencies over wideband conditions. As a result, a succession of highly efficient DPA modes can be formed over a continuous frequency range in the full Doherty region, resulting in a reduced‐size enhanced power efficiency wideband DPA. For verification, a wideband DPA operating from 1.1 to 1.8 GHz was designed and implemented using the proposed topology. The measured drain efficiency of the implemented DPA at 6‐dB back‐off is 52.5%–67.5%, while the saturated power across the specified bandwidth is 43–43.7 dBm. The fabricated DPA exhibits an average efficiency of 48.7%–59.4%, when supplied by a 40‐MHz long‐term evolution (LTE) signal with a 7.5‐dB peak‐to‐average power ratio (PAPR). Performing digital pre‐distortion (DPD) improves the adjacent channel power ratio (ACLR) from −25.8 dBc to −47.6 dBc. 

Design of an efficiency enhanced wideband Doherty power amplifier based on synthesising of a modified harmonic‐control load modulation network

This paper presents a compact wideband power amplifier (PA) that works in a sub-6 GHz frequency band (3 - 4 GHz) for 5G applications. The proposed design of the PA is based on input/output high-order matching networks. The design technique of these matching networks is to compensate for transistor parasitic and packaging components to obtain higher frequency operation. The power amplifier can use this technique to maintain a flat gain of over 11 dB while achieving good input and output-matching performance throughout a wider frequency band. According to the PA performance findings, the proposed PA has an output power of more than 43 dBm throughout a bandwidth of 3 to 4 GHz. The achieved drain efficiency performance of the PA ranges from 63% to 72%. The broadband PA's full size is $\mathbf{75}\times \mathbf{30}\ \mathbf{mm}^{\mathbf{2}}$.

High-Efficiency. 25 Watts Broadband Power Amplifier for Sub-6 GHz 5G

GaN Monolithic Microwave Integrated Amplifiers for Space and Wireless Applications

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GaN Monolithic Microwave Integrated Amplifiers for Space and Wireless Applications