A. Wei
GlobalFoundries
12 Papers
63 Citations
A. Wei is an academic researcher from GlobalFoundries. The author has contributed to research in topics: Transistor & MOSFET. The author has an hindex of 6, co-authored 12 publications.
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Papers
Challenges of analog and I/O scaling in 10nm SoC technology and beyond
A. Wei,Jagar Singh,Guillaume Bouche,Mark A. Zaleski,Rod Augur,B. Senapati,Jason Eugene Stephens,Irene Yuh-Ling Lin,Mahbub Rashed,Lei Yuan,Jongwook Kye,Youngtag Woo,Jia Zeng,Harry J. Levinson,A. Wehbi,P. Hang,V. Ton-That,Kanagala Vijay,D. Yu,D. Blackwell,Adam Beece,Shan Gao,S. Thangaraju,Ramakanth Alapati,Srikanth Samavedam +24 more
- 01 Dec 2014
TL;DR: In the next decade, the focus of SoC innovation will be on patterning and low-resistance materials on the process side, and multi-die package integration on the system side.
16
From the present to the future: Scaling of planar VLSI-CMOS devices towards 3D-FinFETs and beyond 10nm CMOS technologies; manufacturing challenges and future technology concepts
Jan Hoentschel,A. Wei +1 more
- 15 Mar 2015
TL;DR: In this article, 3D-TSVs and inductive coupling as well as proper partitioning will allow the opportunity to beat Moore's Law in the next technology nodes in the future.
10
Advanced SOI CMOS transistor technology for high performance microprocessors
Manfred Horstmann,Maciej Wiatr,A. Wei,Jan Hoentschel,Th. Feudel,Th. Scheiper,Rolf Stephan,M. Gerhadt,Michael Raab +8 more
- 18 Mar 2009
TL;DR: In this paper, an overview of partial depleted Silicon on Insulator (PD SOI) CMOS transistor technologies for high performance microprocessors is presented, which have been developed, applied and optimized for 65/45nm volume manufacturing at GLOBALFOUNDRIES in Dresden.
10
Patent
Methods, apparatus and system for a passthrough-based architecture
Guillaume Bouche,Tuhin Guha Neogi,A. Wei,Jia Zeng,Jongwook Kye,Jason Eugene Stephens,Irene Yuh-Ling Lin,Sudharshanan Raghunathan,Lei Yuan +8 more
- 11 Mar 2016
TL;DR: In this article, a method, apparatus and system for forming a fin-FET device having a pass-through structure is described, where a first gate structure and a second gate structure are formed on a semiconductor wafer.
8
Advanced SOI CMOS transistor technology for high performance microprocessors
Manfred Horstmann,Maciej Wiatr,A. Wei,Jan Hoentschel,Th. Feudel,Th. Scheiper,Rolf Stephan,M. Gerhadt,S. Krügel,Michael Raab +9 more
TL;DR: In this article, the authors present an overview of partially depleted Silicon on Insulator (PD SOI) CMOS transistor technologies for high performance microprocessors, including strained Si, aggressive junction scaling, asymmetric devices, and embedded Si:C.
8