Design and Analysis ofFault-Tolerant Digital Systems: B. W. JOHNSON (Addison Wesley, 1989,577 pp., £41.35) The book provides an introduction to the important aspects of designing fault-tolerant systems, and an evaluation of how well the reliability goals have been achieved. The book is mainly oriented towards a final year undergraduate course on fault-tolerant computing, primarily with an implementation bias. In chapters 1 and 2, definitions and basic terminology are covered, which sets the stage for the remaining chapters, and provides the background and motivation for the remainder of the book. Chapter 3 provides a thorough analysis of fault-tolerance techniques and concepts. This chapter in particular is remarkably well written, covering the issues of hardware and information redundancy, which form the mainstay offault-tolerant computing. Subsequent chapters on the use and evaluation of the various approaches illustrate the principles as they have been put into practice. At the end of chapter 5, small projects that allow the reader to apply the material presented in the preceding chapters are included. The resurgence of interest in fault-tolerance with the emergence of VLSI is the theme of chapter 6, focussing on designing fault-tolerant systems in a VLSI environment. The problems and opportunities presented by VLSI are discussed and the use of redundancy techniques in order to enhance manufacturing yield and to provide in-service reliability are reviewed. The final chapter covers testing, design for testability and testability analysis, which must be considered during each phase of the design process to guarantee that resulting designs can be thoroughly tested. Each chapter is followed by a summary of the key issues and concepts presented therein, and a separate list of references, which makes it easily readable. In addition, there is a reading list with more comprehensive and specialised references devoted to each chapter. Overall, the book is well written, and contains a great deal of information in 577 pages. The book has a definite implementation bias, and draws considerably on the author's experience in industry, particularly reflected in the projects accompanying chapter 5. The book should be a useful addition to a library, and a suitable text to accompany a lecture course on fault-tolerant computing. R. RAMASWAMI, Department ofComputation, UMIST

Book Review: Design and Analysis of Fault-Tolerant Digital SystemsDesign and Analysis of Fault-Tolerant Digital Systems: JohnsonB. W. (Addison Wesley, 1989, 577 pp., £41.35)

A new design methodology for a pattern generator is proposed, formulated in the context of on-chip BIST. The design methodology is circuit-specific and uses synthesis techniques to design BIST generators. The pattern generator consists of two components: a pseudorandom pattern generator (like an LFSR or, preferably, a GLFSR) and a combinational logic to map the outputs of the pseudorandom pattern generator. This combinational logic is synthesized to produce a given set of target patterns by mapping the outputs of the pseudorandom pattern generator. It is shown that, for a particular CUT, an area-efficient combinational logic block can be designed/synthesized to achieve 100 (or almost 100) percent single stuck-at fault coverage using a small number of test the This method is significantly different from weighted pattern generation and can guarantee testing of all hard-to-detect faults without expensive test point insertion. Experimental results on common benchmark netlists demonstrate that the fault coverage of the proposed pattern generator is significantly higher compared to conventional pattern generation techniques. The design technique for the logic mapper is unique and can be used effectively to improve existing pattern generators for combinational logic and scan-based BIST structures.

A BIST pattern generator design for near-perfect fault coverage

System-on-Chip (SOC) designs use numerous and diverse embedded cores and memories. Very high system reliability requirements mandate greater than 99.9% ATPG chip manufacturing test coverage. Logic BIST and memory BIST are increasingly used for high system test coverage with additional constraints that some cores or pockets of user designed logic have to be functionally active during BIST. This paper describes the challenges of a design methodology to handle such SOC designs and the automated solutions that address these problems.

A building block BIST methodology for SOC designs: a case study

A new ad-hoc technique to select the proper seed and the number of the random test patterns to be generated is presented. This technique uses an offline algorithm to search and classify the random patterns based on the deterministic test patterns generated by the automatic test pattern generator (ATPG). The seed activated linear feedback shift register (LFSR) generates exhaustive test patterns which are applied on any design under test (DUT). The responses are received at the output of the scan chains in the DUT and they are compressed to produce a signature. It is shown that this scheme produces the same fault coverage with lesser number of random test patterns than an arbitrary seed. Also, this technique helps to estimate the number of BIST test patterns to be generated to achieve specific fault coverage. Results on six ISCAS-89 designs with the help of Cadence Encounter true time 13.1 ATPG is shown.

Deterministic seed selection and pattern reduction in Logic BIST

An apparatus with a generator to generate a pattern and multiple scan chains (110) configured to receive the pattern from the generator. Multiple signature registers (116, 118) coupled to the scan chains, to receive an output of at least one of scan chains during a mode of the integrated device.

Method and apparatus for fault tolerant and flexible test signature generator

Test Structure Verification (TSV) is the process used to assess the conformance of a circuit to a set of predefine Design For Testability (DFT) rules. Test generation algorithms are typically optimized for circuits that are highly testable, so Test Structure Verification (TSV) ultimately indicates the overall testability of a circuit. Logical BIST (Built In Self Test) is a methodology based on signature analysis which produces patterns used to identify the correctness of the manufactured circuit via specially designed BIST hardware. This paper describes a set of proven production level procedures used to identify and verify the test structure and behavior of BIST hardware. These algorithms are based on the TSV implementation of IBM's TestBench test generation system.

Test structure verification of logical BIST: problems and solutions

Signature Based Test Generation continues to grow in importance as VLSI circuits cross and leap beyond the multi-million gate mark. The Logic Built-In Self Test (LBIST) methodology is a signature analyst's based test generation strategy in wide spread use today. Since the LBIST hardware forms the basis for the generation of test patterns and failure-mode diagnostics, it is paramount that the LBIST test structures conform to LBIST methodology requirements. If the LBIST structures are modeled incorrectly, then pattern mismatches may occur at the tester. This paper describes a set of production level algorithms and procedures used to validate the LBIST structures used in the LBIST methodology. The validation includes the identification and verification of individual components of the LBIST structure. These algorithms are based on the test structure validation processes designed within IBM's TestBench test generation system.

An automatic validation methodology for logic BIST in high performance VLSI design

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Test structure verification of logical BIST: problems and solutions

An automatic validation methodology for logic BIST in high performance VLSI design