GaN-on-Si power switching transistors that use carbon-doped epitaxy are highly vulnerable to dynamic $\text{R}_{ON}$ dispersion, leading to reduced switching efficiency. In this paper, we identify the causes of this dispersion using substrate bias ramps to isolate the leakage paths and trapping locations in the epitaxy and simulation to identify their impact on the device characteristics. It is shown that leakage can occur both vertically and laterally, and we suggest that this is associated not only with bulk transport, but also with extended defects as well as hole gases at heterojunctions. For exactly the same epitaxial design, it is shown using a “leaky dielectric” model that depending on the leakage paths, dynamic $\text{R}_{ON}$ dispersion can vary between insignificant and infinite. An optimum leakage configuration is identified to minimize dispersion requiring a resistivity which increases with depth in the buffer stack. It is demonstrated that leakage through the undoped GaN channel is required over the entire gate to drain gap, and not just under the contacts, in order to fully suppress dispersion.

/pdf/leaky-dielectric-model-for-the-suppression-of-dynamic-r-2ho0i94ufm.pdf

“Leaky Dielectric” Model for the Suppression of Dynamic $R_{\mathrm{ON}}$ in Carbon-Doped AlGaN/GaN HEMTs

The development of GaN-on-diamond devices holds much promise for the creation of high-power density electronics. Inherent to the growth of these devices, a dielectric layer is placed between the GaN and diamond, which can contribute significantly to the overall thermal resistance of the structure. In this work, we explore the role of different interfaces in contributing to the thermal resistance of the interface of GaN/diamond layers, specifically using 5 nm layers of AlN, SiN, or no interlayer at all. Using time-domain thermoreflectance along with electron energy loss spectroscopy, we were able to determine that a SiN interfacial layer provided the lowest thermal boundary resistance (<10 m2K/GW) because of the formation of an Si–C–N layer at the interface. The AlN and no interlayer samples were observed to have TBRs greater than 20 m2K/GW as a result of a harsh growth environment that roughened the interface (enhancing phonon scattering) when the GaN was not properly protected.

Low Thermal Boundary Resistance Interfaces for GaN-on-Diamond Devices

We present a GaN monolithic inverter IC on Si substrate and successful motor-drive by it for the first time. Taking advantages of the bi-directional operation free from the forward voltage off-set [1], the inverter can be operated just by the integrated six GaN-based normally-off gate injection transistors (GITs) without any external fast recovery diodes (FRDs) to flow the fly-wheel current. The IC enables the efficiency as high as 93% at low power operation where so far that of conventional Si-based inverters has remained lower value owing to the forward voltage off-set. The key processing technology is the newly introduced planar isolation using Fe ion implantation which fully isolates the GaN-based lateral devices each other.

GaN Monolithic Inverter IC Using Normally-off Gate Injection Transistors

In carbon-doped GaN (GaN:C) buffers used in a GaN-on-Si technology, the buffer is embedded in between transition and channel layers. This makes the analysis of buffer properties difficult due to e.g., carrier injection from or potential drop at these adjacent layers. Here, we analyze capacitance- and current-voltage characteristics of 200–300 nm thick GaN:C ([C] = 1019 cm−3) layers which are embedded between a top metal electrode and bottom n-doped GaN (n-GaN). Such structures allow a better potential control in GaN:C and thus determination of the band diagram quantitatively. The accumulation of negative charge (concentration up to 6 × 1017 cm−3) with bias is observed in GaN:C at both polarities. For biases Vappl   +1.7 V, accumulated negative charges in GaN:C raise an energy barrier of ∼1.1 eV for electron injection from n-GaN ...

The interplay of blocking properties with charge and potential redistribution in thin carbon-doped GaN on n-doped GaN layers

In this article, we investigate the impact of hard-switching on the dynamic ON-resistance ( ${R}_{ \mathrm{ ON}}$ ) in the AlGaN/GaN high-electron mobility transistors (HEMTs). The pulsed measurements were taken on a set of GaN-on-Si wafers, showing a significant ${R}_{ \mathrm{ ON}}$ increase after hard-switching compared with soft-switching. The impact of hard-switching was found to be strongly dependent on the surface passivation stoichiometry. Both hot electrons and self-heating are generated during hard-switching and they were investigated separately. For the self-heating effect, we found that the heating energy dissipated during hard-switching followed a different trend to the dynamic ${R}_{ \mathrm{ ON}}$ , showing that self-heating was not responsible for the dynamic ${R}_{ \mathrm{ ON}}$ . Following hard-switching, we found that the recovery of the ${R}_{ \mathrm{ ON}}$ occurred on a time scale of microseconds, far too fast to be explained by buffer trapping. Consequently, we suggest that the hard-switching-induced hot electrons are trapped on the surface and result in the dynamic ${R}_{ \mathrm{ ON}}$ . To support these conclusions, we undertook 2-D-TCAD simulations. Self-heating was found to be incompatible with the measurements, and surface-trapped hot electrons during hard-switching were shown to be consistent with the experimental observation. Based on the analysis, we find that modifying the field plates and stoichiometries of SiN x can be the possible solutions to suppress dynamic ${R}_{ \mathrm{ ON}}$ after hard-switching.

The Impact of Hot Electrons and Self-Heating During Hard-Switching in AlGaN/GaN HEMTs

Although astounding performance is already proven by many research papers, the widespread adoption of GaN power devices in the market is still hampered by (1) yield and reproducibility ; (2) cost ; (3) reliability. All three factors are to be considered, but to convince customers to adopt GaN power devices, proven device and product reliability is a must. Cost is kept acceptably low by growing the GaN epi stack on 6 inch and 8inch Si substrates, and by processing the GaN power device technology in standard CMOS production lines. This paper will focus on the most important intrinsic reliability mechanisms for GaN power devices. It will cover gate dielectric reliability, Ohmic contact reliability, accelerated drain stress testing (high temperature reverse bias--HTRB) and high voltage device wear-out testing (high voltage off-state stress--HVOS). Acceleration models are discussed A measurement strategy to extract valuable information about the physical properties of the buffer layers (e.g. activation energies of the traps, conduction mechanisms, ...) based on simple transmission line structures, is outlined.

/pdf/invited-intrinsic-reliability-assessment-of-650v-rated-algan-1aizwxzw3e.pdf

(Invited) intrinsic reliability assessment of 650V rated AlGaN/GaN based power devices: an industry perspective

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(Invited) intrinsic reliability assessment of 650V rated AlGaN/GaN based power devices: an industry perspective