It is shown that the charge pumping technique is able not only to determine the degradation mechanisms in MOS transistors under all kinds of aging conditions (eg, irradiation, hot-carrier, Fowler-Nordheim stress), but also in several cases to evaluate and to quantify the degradation It is further shown that the technique can be applied to separate the presence of fixed oxide changes due to charge trapping and the generation of interface traps It can be used to analyze degradations that occur uniformly over the transistor channel, as well as strongly localized transistor degradations (eg, for the case of hot-carrier degradations) All possible cases of uniform and nonuniform degradations, for p-channel as well as for n-channel transistors, are described, and for most of them experimental examples are given >

Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation

The lucky-electron concept is successfully applied to the modeling of channel hot-electron injection in n-channel MOSFET's, although the result can be interpreted in terms of electron temperature as well. This results in a relatively simple expression that can quantitatively predict channel hot-electron injection current in MOSFET's. The model is compared with measurements on a series of n-channel MOSFET's and good agreement is achieved. In the process, new values for many physical parameters such as hot-electron scattering mean-free-path, impact-ionization energy are determined. Of perhaps even greater practical significance is the quantitative correlation between the gate current and the substrate current that this model suggests.

Lucky-electron model of channel hot-electron injection in MOSFET'S

This paper presents a comparison of hot-carrier degradation experiments with simulations of hot electron and hole emission into the oxide. It is shown that both the emission of holes and of electrons are essential to explain the dominant generation of negative charge by a new degradation mechanism. Moreover, a peak of positive-charge generation at a gate voltage close to threshold was found in our experiments which is due to hole trapping. A simple degradation model based on the calculated electron and hole emission is presented which gives a very good description of the observed behavior of degradation effects.

Hot-electron and hole-emission effects in short n-channel MOSFET's

The phenomenon of and the physical mechanisms for the generation of minority carriers in the substrate of NMOS and CMOS are studied Secondary impact ionization is not responsible The responsible mechanisms are hot-electron-induced photocarrier generation and, under extreme conditions, forward biasing of the source-substrate junction The photon generation is believed to be due to the bremsstrahlung of the channel hot electrons A theoretical model based on the lucky electron concept and the bremsstrahlung mechanism is proposed The calculated characteristics of photon generation agree well with experimental results About 2 × 10-5photogenerated minority carriers are generated for every (primary) impact-ionization event in NMOSFET Photocarrier-induced leakage current can be fitted with either an inverse square dependence on distance or an exponential dependence with an effective decay length of about 780 µm

Hot-electron-induced photon and photocarrier generation in Silicon MOSFET's

After defining the multiplication factor and the ionization rate together with their interrelationship, multiplication and breakdown models for diodes and MOS transistors are discussed. Different ionization models are compared and test structures are discussed for measuring the multiplication factor accurately enough for reliable extraction of the ionization rates. Multiplication measurements at different temperatures are performed on a bipolar NPN transistor, and yield new electron ionization rates at relatively low electrical fields. An explanation for the spread of the experimental values of the existing data on ionization rate is given. A new implementation method for a local avalanche model into a device simulator is presented. The results are less sensitive to the chosen grid size than the ones obtained from the existing method.

/pdf/impact-ionization-in-silicon-a-review-and-update-2nmz801knv.pdf

Impact ionization in silicon: A review and update

We describe a user-oriented software tool-MINIMOS-for the two-dimensional numerical simulation of planar MOS transistors. The fundamental semiconductor equations are solved with sophisticated programming techniques to allow very low computer costs. The program is able to calculate the doping profiles from the technological parameters specified by the user. A new mobility model has been implemented which takes into account the dependence on the impurity concentration, electric field, temperature, and especially the distance to the Si-SiO 2 interface. The power of the program is shown by calculating the two-dimensional internal behavior of three MOST's with 1-µm gate length differing in respect to the ion-implantation steps. In this way, the threshold voltage shift by a shallow implantation and the suppression of punchthrough by a deep implantation are demonstrated. By calculating the output characteristics without and with mobility reduction, the essential influence of this effect is shown. From the subthreshold characteristics, the suppression of short-channel effects by ion implantation becomes apparent. The MINIMOS program is available for everyone for just the handling costs.

/pdf/minimos-a-two-dimensional-mos-transistor-analyzer-3m4br8ajbp.pdf

MINIMOS&#8212;A two-dimensional MOS transistor analyzer

We describe a user-oriented software tool-MINIMOS-for the two-dimensional numerical simulation of planar MOS transistors. The fundamental semiconductor equations are solved with sophisticated programming techniques to allow very low computer costs. The program is able to calculate the doping profiles from the technological parameters specified by the user. A new mobility model has been implemented which takes into account the dependence on the impurity concentration, electric field, temperature, and especially the distance to the Si-SiO/sub 2/ interface. The power of the program is shown by calculating the two-dimensional internal behavior of three MOST's with 1-/spl mu/m gate length differing in respect to the ion-implantation steps. In this way, the threshold voltage shift by a shallow implantation and the suppression of punch through by a deep implantation are demonstrated. By calculating the output characteristics without and with mobile reduction, the essential influence of this effect is shown. From the sub-threshold characteristics, the suppression of short-channel effects by ion implantation becomes apparent. The MINIMOS program is available for everyone for just the handling costs.

/pdf/minimos-a-two-dimensional-mos-transistor-analyzer-4nbzjz7xho.pdf

MINIMOS - A Two-Dimensional MOS Transistor Analyzer

A two-dimensional self consistent MOS transistor model accounting for the avalanche effect is described. The classical semiconductor equations—Poisson's equation and the two carrier equations—are solved with the finite difference method. The pair production rate is evaluated at any mesh point and dominates the inhomogeneity term of the carrier continuity equations in case of avalanche. Calculated and measured current-voltage characteristics are in good agreement and thus support our model. For a 3 μm device the electrical potential, the carrier densities, and the generation rates are shown in quasi three-dimensional plots from which the avalanche generation in the pinch-off region becomes apparent. Furthermore, hole storage close to the interface is seen to take place in the channel up to the vicinity of the source region. The corresponding barrier lowering leads to increased electron injection from the source and enhanced avalanche. The barrier lowering is supported by the influence of the parasitic bulk resistance.

A two-dimensional model of the avalanche effects in MOS transistors

A strategy to examine the sensitivity of electrical device parameters on geometrical and technological tolerances is described. An approach is offered to determine the limit of device miniaturzation for a given fabrication process and a desired operating condition. As a didactic example of practical relevance the minimum channel length for a modern silicon gate, double implant process due to threshold uncertainty is estimated. A method to calculate global sensitivity numbers for the reproducability of miniaturized devices is suggested. As an experimental determination of sensitivities is extremely difficult and expensive, numerical simulations are ideally suited for this purpose.

/pdf/investigation-of-parameter-sensitivity-of-short-channel-5bghoqiyl1.pdf

Investigation of parameter sensitivity of short channel mosfets

An accurate two-dimensional self-consistent numerical model for MOS transistors which is able to predict avalanche behavior is presented. This model aims at a more principal understanding of the physical processes which arise from the avalanche effect and which eventually lead to breakdown. The system of the fundamental semiconductor equations with several generation/recombination mechanisms is solved. To improve the description of the ionization process, correction terms are introduced which account for the fact that the gate induced field does not cause ionization. Holes which are generated in the pinch-off region by impact ionization cause a bulk current; the voltage drop at the parasitic bulk resistance initiates an internal feedback mechanism. Thus a negative resistance branch of the drain current characteristic can arise. However, at high current levels, introduced by a high gate bias and/or a short channel, this snap-back effect is often counterbalanced by strong recombination. Snapback voltage can be estimated with this model.

Analysis of Breakdown Phenomena in MOSFET's

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MINIMOS—A two-dimensional MOS transistor analyzer

MINIMOS - A Two-Dimensional MOS Transistor Analyzer

A two-dimensional model of the avalanche effects in MOS transistors

Investigation of parameter sensitivity of short channel mosfets

Analysis of Breakdown Phenomena in MOSFET's

A. Schutz

Author Tools

Chat about Author

Papers

MINIMOS&#8212;A two-dimensional MOS transistor analyzer

MINIMOS - A Two-Dimensional MOS Transistor Analyzer

A two-dimensional model of the avalanche effects in MOS transistors

Investigation of parameter sensitivity of short channel mosfets

Analysis of Breakdown Phenomena in MOSFET's

MINIMOS—A two-dimensional MOS transistor analyzer