To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

Nonvolatile memory structures and fabrication methods

The poly-to-poly tunneling characteristics in the third-generation SuperFlash memory cell have been analyzed. It has been demonstrated that, even without a sharp floating-gate (FG) tip, the cell still demonstrates the main features of the erase process from previous SuperFlash generations, namely, corner (tip)-enhanced tunneling, asymmetry of the tunneling voltage in forward and reverse directions, strong localization of the tunneling process, and effective suppression of anode hole injection. Furthermore, a new method for measuring the tunneling voltage on a regular FG cell is described. The reliability aspects of corner-enhanced tunneling in the SuperFlash cell are also discussed.

Floating-Gate Corner-Enhanced Poly-to-Poly Tunneling in Split-Gate Flash Memory Cells

In a nonvolatile memory cell having at least two floating gates, each floating gate ( 160 ) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate ( 140 ). The spacer can be formed from a layer ( 160.2 ) deposited after the layer ( 160.1 ) which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are present in both portions. The control gate ( 170 ) can be defined without photolithography. Other embodiments are also provided.

Nonvolatile memory cell with multiple floating gates formed after the select gate and having upward protrusions

Replica-cell sensing schemes are commonly used in the read circuits of flash memories to provide the appropriate reference current across various process, voltage and temperature (PVT) conditions. However, process variation on the replica array causes fluctuations in the settling time and the value of the reference current across dies or wafers, especially in split-gate flash memories. A long settling time of reference current slows down the access time, and causes ringing on outputs. Fluctuation in the reference current produces various sensing margins, and decreases the yield, due to tail bits. A circuit-level technique for embedded flash memories, called pre-stable current sensing (PSCS), is proposed to reduce the fluctuation in access time and sensing margin, without additional masks or process steps. Experiments on fabricated flash macros (4 Mb, 2 Mb, 1 Mb, and 512 Kb) using a 0.25 mum embedded flash process demonstrate that PSCS achieves uniform access time across hundreds of samples. Additionally, PSCS works with a wide range of supply voltages (1.1-3 V).

A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme

In a memory cell ( 110 ) having multiple floating gates ( 160 ), the select gate ( 140 ) is formed before the floating gates. In some embodiments, the memory cell also has control gates ( 170 ) formed after the select gate. Substrate isolation regions ( 220 ) are formed in a semiconductor substrate ( 120 ). The substrate isolation regions protrude above the substrate. Then select gate lines ( 140 ) are formed. Then a floating gate layer ( 160 ) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric ( 164 ) is formed over the floating gate layer, and a control gate layer ( 170 ) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates ( 160 ). A dielectric layer ( 164 ) overlying the floating gate has a continuous feature that overlies the floating gate and also overlays a sidewall of the select gate ( 140 ). Each control gate ( 160 ) overlies the continuous feature of the dielectric layer and also overlies the floating gate. In another aspect, substrate isolation regions ( 220 ) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

Nonvolatile memory cell with multiple floating gates formed after the select gate

A split-gate flash memory cell has been embedded in a 0.18 um high performance CMOS logic process with copper interconnects. A novel triple self-aligned (SA3) process provides a compact cell and high degree of modularity. The entire memory cell structure is defined with one single mask in an area less than 13F/sup 2/. Source-side channel hot electron program and poly-poly tunneling erase enable low power consumption suitable for low voltage applications.

0.18 um modular triple self-aligned embedded split-gate flash memory

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0.18 um modular triple self-aligned embedded split-gate flash memory