A. Scheit
5 Papers
A. Scheit is an academic researcher. The author has contributed to research in topics: Engineering & Focused ion beam. The author has an hindex of 3, co-authored 4 publications.
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Papers
SiGe HBT with fx/fmax of 505 GHz/720 GHz
Bernd Heinemann,Holger Rucker,R. Barth,F. Barwolf,J. Drews,Gunter Fischer,A. Fox,O. Fursenko,Thomas Grabolla,Frank Herzel,Jens Katzer,J. Korn,A. Kruger,P. Kulse,T. Lenke,Marco Lisker,Steffen Marschmeyer,A. Scheit,D. Schmidt,J. Schmidt,M. A. Schubert,Andreas Trusch,C. Wipf,D. Wolansky +23 more
- 01 Dec 2016
TL;DR: An experimental SiGe HBT technology featuring fT/fmax/BVCEO = 505 GHz/720 GHz/1.6 V and a minimum CML ring oscillator gate delay of 1.34 ps is presented in this article.
193
Resistive switching behavior in TiN/HfO 2 /Ti/TiN devices
Damian Walczyk,T. Bertaud,Malgorzata Sowinska,M. Lukosius,M. A. Schubert,A. Fox,Dirk Wolansky,A. Scheit,Mirko Fraschke,Gunter Schoof,C. Wolf,Rolf Kraemer,Bernd Tillack,R. Korolevych,Valeriy Stikanov,Ch. Wenger,Thomas Schroeder,Ch. Walczyk +17 more
- 26 Nov 2012
TL;DR: In this paper, the bipolar resistive switching behavior of more than 100 back-end-of-line (BEOL) integrated 600×600nm2 TiN/HfO 2 /Ti/TiN MIM devices in a 4 kbit memory array was investigated.
24
Modular integration of annular TSV structures filled with tungsten in a 0.25µm SiGe
S. Marschmeyer,J. Berthold,A. Kruger,M. Lisker,A. Scheit,Sebastian Schulze,Andreas Trusch,Matthias Wietstruck,D. Wolansky +8 more
TL;DR: In this paper, an annular TSV structure filled with tungsten was integrated in a BiCMOS technology, and the impact of TSV fabrication on the performance of MOS transistors was investigated.
10
Low-temperature monitoring with implantation and alloying
L. Van Den Ende,Michael Grund,Uwe Schwarz,C. Preiß,Volker Götz,Sarala Ramasubramanian,J. Niess,Wilfried Lerch,A. Scheit +8 more
TL;DR: In this article , a complex monitoring process for low temperature processing by a defined implantation condition and an alloying method capable of monitoring processes at temperatures below 600°C to ensure the process requirements of the manufacturing flow is presented.
Detection and reduction of via faults
D. Wolansky,Joachim Bauer,U. Haak,W. Hoppner,Jens Katzer,P. Kulse,Andreas Mai,H. Rucker,A. Scheit,K. Schulz +9 more
- 26 Nov 2012
TL;DR: In this article, a methodology for fast detection of via faults is presented, which uses parametric tester for resistance measurements, a CD-SEM for voltage contrast inspection and defect localization, and focused ion beam (FIB) preparation for failure analysis.