Design of the binary logic circuits is limited by the requirement of the interconnections. A possible solution could be arrived at by using a larger set of signals over the same chip area. Multiple-valued logic (MVL) designs are gaining importance from that perspective. This paper presents two types of multiple-valued full adder circuits, implemented in Multiple-Valued voltage-Mode Logic (MV-VML). First type is designed using one hot encoding and barrel shifter. Second full adder circuit is designed by converting the quaternary logic in to unique code, which enables to implement circuit with reduced hard ware. Sum and carry are processed in two separate blocks, controlled by code generator unit. The design is targeted for the 0.18 µm CMOS technology and verification of the design is done through Synopsis HSPICE and COSMOSCOPE Tools. Area of the designed circuits is less than the corresponding binary circuits and quaternary adders because number of transistors used are less.

/pdf/design-of-high-performance-quaternary-adders-gxvrmnqc26.pdf

Design of High Performance Quaternary Adders

In this paper, the design and implementation of an analog sigmoid neuron is presented. The activation function of the proposed neuron is implemented based on the piecewise linear approximation in the analog domain. The proposed neuron provides the required accuracy that cannot be achieved in general by analog neural network implementations. General digital outputs of a sigmoid neuron are replaced with fewer analog digits of the continuous valued number system (CVNS), while at the same time maximum approximation error is kept the same as the digital architectures. The proposed CVNS neuron resulted in an optimal ASIC implementation and is suitable for neurochips with on-chip learning. The VLSI implementation of the neuron is carried out using current-mode circuits. The implementation results compare favorably with previously developed structures in terms of area, delay, and power consumption. The proposed neuron structure occupies 28% less area compared with the state-of-the-art methods and it has two times lower power $\times $ delay.

An Analog CVNS-Based Sigmoid Neuron for Precise Neurochips

/pdf/design-of-high-performance-quaternary-adders-2a1286darx.pdf

In this paper, design of a mixed-signal 64-bit adder based on the continuous valued number system (CVNS) is presented. The 64-bit adder is generated by cascading four 16-bit radix-2 CVNS adders. Truncated summation of the CVNS digits reduced the number of required interconnections in the system, which in turn reduced design complexity and hardware costs. This adder can perform one 64-bit, two 32-bit, four 16-bit, or eight 8-bit additions on demand for media signal processing applications. The compact and low-power and low-noise design of the adder is suitable for this type of application. The 64-bit adder designed in TSMC CMOS 0.18-mum technology, has a worst case delay of 1.5 ns, energy dissipation of about 14 pJ with the core area of 13 250mum2.

Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing

Binary multiplication is one of the fundamental arithmetic operations, and it is used in digital filters and signal processing applications. The continuous valued number system (CVNS) is a recently introduced number system that allows digital arithmetic, with arbitrary precision, to be implemented with analog circuitry. Due to the analog nature of the numbers system, CVNS reduces the total system and cross talk noise. An 8 times 8 digital multiplier is proposed, using CVNS compressors for reducing the digital partial products. A new definition for the CVNS compressor for the first time is introduced, along with a novel CMOS current mode circuit. The multiplier is realized in TSMC CMOS 0.18mum technology, with a maximum delay of 900ps, static power consumption of 19mW and a core area of 11200 mum2. The example demonstrates that CVNS designs can yield fast, low power arithmetic circuits using low noise analog circuitry.

Digital Multiplication using Continuous Valued Digits

This paper presents a novel number system based on signed continuous valued digits. Arithmetic operations in this number system are performed using simple analog circuitry, in contrast to the conventional implementation of arithmetic units by Boolean or multiple-valued logic circuits. Unlike the limited precision offered by classical analog arithmetic circuits, the ensemble of continuous valued digits that comprises a number in this system provides arbitrary implementation precision with standard analog circuitry. The number system also provides almost-carry-free arithmetic structures with digit level redundancy. In this paper, we introduce the mathematical foundations for positive and negative numbers, addition, multiplication, redundancy, radix conversions, and also the digit value integrity for circuit implementations. Potential applications are in the area of low noise and low cross-talk circuitry for arithmetic circuits used in mixed-signal systems.

A number system with continuous valued digits and modulo arithmetic

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A number system with continuous valued digits and modulo arithmetic