A. Ray
IBM
5 Papers
112 Citations
A. Ray is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Silicon on insulator. The author has an hindex of 4, co-authored 5 publications.
Chat about Author
Papers
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
Effendi Leobandung,H. Nayakama,Dan Mocuta,K. Miyamoto,M. Angyal,H.V. Meer,K. McStay,Ishtiaq Ahsan,Scott D. Allen,Atsushi Azuma,Michael P. Belyansky,R.-V. Bentum,J. Cheng,Dureseti Chidambarrao,B. Dirahoui,M. Fukasawa,M. Gerhardt,Michael A. Gribelyuk,Scott Halle,H. Harifuchi,D. Harmon,J. Heaps-Nelson,H. Hichri,K. Ida,M. Inohara,I.C. Inouc,Keith Jenkins,T. Kawamura,Byeong Y. Kim,S.-K. Ku,Mahender Kumar,S. Lane,Lars W. Liebmann,R. Logan,I. Melville,K. Miyashita,Anda Mocuta,P. O'Neil,M.-F. Ng,Takeshi Nogami,A. Nomura,Christine Norris,E. Nowak,Mizuki Ono,Siddhartha Panda,C. Penny,Carl J. Radens,Ravikumar Ramachandran,A. Ray,S.-H. Rhee,D. Ryan,T. Shinohara,G. Sudo,F. Sugaya,Jay W. Strane,Y. Tan,L. Tsou,L. K. Wang,F. Wirbeleit,S. Wu,Tenko Yamashita,H. Yan,Q. Ye,D. Yoneyama,D. Zamdmer,Huicai Zhong,Huilong Zhu,Wenjuan Zhu,Paul D. Agnello,Scott J. Bukofsky,Gary B. Bronner,Emmanuel F. Crabbe,G. Freeman,Shih-Fen Huang,T. Ivers,H. Kuroda,D. McHerron,J. Pellerin,Yoshiaki Toyoshima,S. Subbanna,N. Kepler,L. Su +81 more
- 14 Jun 2005
TL;DR: In this article, a high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels.
76
A high-performance 0.08 /spl mu/m CMOS
L. Su,S. Subbanna,Emmanuel F. Crabbe,Paul D. Agnello,E. Nowak,R. Schulz,Stewart E. Rauch,Hung Y. Ng,T. Newman,A. Ray,M. Hargrove,A. Acovic,J. Snare,S. Crowder,Bomy A. Chen,J.Y.-C. Sun,Bijan Davari +16 more
- 11 Jun 1996
TL;DR: In this paper, the authors demonstrate a 0.08 /spl mu/m CMOS suitable for high-performance (V/sub dd/=1.8 V) and low-power applications (Vsub dd < 1.5 V) with the best current drive at a given off-current reported in the literature to date.
23
Silicon-on-Insulator MOSFETs with Hybrid Crystal Orientations
Min Yang,Kevin K. Chan,Amit Kumar,S.-H. Lo,Jeffrey W. Sleight,Leland Chang,R G Rao,Stephen W. Bedell,A. Ray,John A. Ott,J.G. Patel,D'Emic +11 more
- 02 Oct 2006
TL;DR: In this article, a novel silicon-on-insulator (SOI) structure was presented on hybrid orientation substrates (SuperHOT), i.e. with nFETs on (100) surface orientation and pFET on (110) orientation, using silicon lateral overgrowth.
10
Effective Schottky Barrier lowering for contact resistivity reduction using silicides as diffusion sources
Zhen Zhang,Francois Pagette,Christopher P. D'Emic,Bin Yang,Christian Lavoie,A. Ray,Yu Zhu,Marinus Hopstaken,Siegfried L. Maurer,Conal E. Murray,M. Guillorn,D. Klaus,J.J. Bucchignano,John Bruley,John A. Ott,A. Pyzyna,J. Newbury,W. Song,G. Zuo,K.-L. Lee,Ahmet S. Ozcan,J. Silverman,Q.C. Ouyang,D-G. Park,Wilfried Haensch,Paul M. Solomon +25 more
- 26 Apr 2010
TL;DR: In this paper, the Schottky Barrier Height (SBH) tuning was used to reduce the contact resistance of NiPt silicide to 7×10−9 Ω-cm2.
4
High performance and highly stable ultra-thin oxynitride for CMOS applications
Wenjuan Zhu,Joseph F. Shepard,Wei He,A. Ray,Paul Ronsheim,Dominic J. Schepis,Dan Mocuta,Effendi Leobandung +7 more
- 30 Dec 2008
TL;DR: In this paper, a pre-conditioning process in plasma nitridation process was proposed to reduce the wafer-to-wafer variation for nitrogen and oxygen dose in the ultra-thin gate dielectrics.