Successful measurements, applying the EBP to the backside of thinned circuitry, using test structures and commercial chips have been demonstrated In addition to the well known CCVC a new contrast mechanism named space charge coupled voltage contrast (SCCVC) was detected, which strongly increased the EBP signal measured directly on the transistor source or drain regions Therefore, measurements are possible as long as the electron beam can be placed on a transistor well area, which is larger than the lower metal lines by a factor of 3 The voltage signal has been produced correctly with 100mV noise margin on one of the test structures and since the coplanarity of the trench bottom to silicon surface is excellent, the same accuracy can be expected for any DUT when the process is properly calibrated As a result, the presented method is very promising since the lateral resolution potential of an EBP system is only limited by the low energy E-beam diameter Improvements in this field have not been used to enhance EBP in recent years but even with the present systems, measurements on sub-50nm technology seem to be possible Furthermore, optical methods are struggling with their resolution limits and therefore backside EBP can become a very powerful method in the near future

Functional IC analysis through chip backside with nano scale resolution - E-beam probing in FIB trenches to STI level

. Physical analysis for IC functionality in submicron technologies requires access through chip backside. Based upon typical global backside preparation with 50–100 µm moderate silicon thickness remaining, a state of the art of the analysis techniques available for this purpose is presented and evaluated for functional analysis and layout pattern resolution potential. A circuit edit technique valid for nano technology ICs, is also presented that is based upon the formation of local trenches using the bottom of Shallow Trench Isolation (STI) as endpoint for Focused Ion Beam (FIB) milling. As a derivative from this process, a locally ultra thin silicon device can be processed, creating a back surface as work bench for breakthrough applications of nanoscale analysis techniques to a fully functional circuit through chip backside. Several applications demonstrate the power and potential of this new approach.

/pdf/physical-ic-debug-backside-approach-and-nanoscale-challenge-3fo1smj80i.pdf

Physical IC debug – backside approach and nanoscale challenge

IC debug with E-beam probing is presented in an innovative application accessing the active device directly from chip backside after FIB preparation. The potential of this approach in nanoscale and gigahertz dimensions is evaluated.

Backside E-Beam Probing on Nano scale devices

Physical analysis, trimming and editing of nanoscale IC function with backside FIB processing

Contact to contacts or silicide by use of backside FIB circuit edit allowing to approach every active circuit node

Parallel thinning of silicon, close to active devices, is a risk potential specific to back side editing. Monitored FETs and ring oscillators showed no significant performance change for various remaining silicon thicknesses down to SOI-like structures

Impact of back side circuit edit on active device performance in bulk silicon ICs

Electrical Performance Evaluation of FIB Edited Circuits through Chip Backside Exposing Shallow Trench Isolations

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Impact of back side circuit edit on active device performance in bulk silicon ICs

Electrical Performance Evaluation of FIB Edited Circuits through Chip Backside Exposing Shallow Trench Isolations