The CMOS image sensor computes two-dimensional convolution of video frames with a programmable digital kernel of up to 8 times 8 pixels in parallel directly on the focal plane. Three operations, a temporal difference, a multiplication and an accumulation are performed for each pixel readout. A dual-memory pixel stores two video frames. Selective pixel output sampling controlled by binary kernel coefficients implements binary-analog multiplication. Cross-pixel column-parallel bit-level accumulation and frame differencing are implemented by switched-capacitor integrators. Binary-weighted summation and concurrent quantization is performed by a bank of column-parallel multiplying analog-to-digital converters (MADCs). A simple digital adder performs row-wise accumulation during ADC readout. A 128 times 128 active pixel array integrated with a bank of 128 MADCs was fabricated in a 0.35 mum standard CMOS technology. The 4.4 mm times 2.9 mm prototype is experimentally validated in discrete wavelet transform (DWT) video compression and frame differencing.

/pdf/focal-plane-algorithmically-multiplying-cmos-computational-3k4vaushmp.pdf

Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor

In this paper, we introduce our CMOS block MAtrix Transform Imager Architecture (MATIA). This imager is capable of performing programmable matrix operations on an image. The imager architecture is both modular and programmable. The pixel used in this architecture performs matrix multiplication while maintaining a high fill factor (46%), comparable to active pixel sensors. Floating gates are used to store the arbitrary matrix coefficients on-chip. The chip operates in the subthreshold domain and thus has low power consumption (80 /spl mu/W/frame). We present data for different convolutions and block transforms that were implemented using this architecture, and also present data from baseline JPEG and motion JPEG systems which we have implemented using MATIA.

MATIA: a programmable 80 /spl mu/W/frame CMOS block matrix transform imager architecture

A prototype of a 34 /spl times/ 34 pixel image sensor, implementing real-time analog image processing, is presented. Edge detection, motion detection, image amplification, and dynamic-range boosting are executed at pixel level by means of a highly interconnected pixel architecture based on the absolute value of the difference among neighbor pixels. The analog operations are performed over a kernel of 3 /spl times/ 3 pixels. The square pixel, consisting of 30 transistors, has a pitch of 35 /spl mu/m with a fill-factor of 20%. The chip was fabricated in a 0.35 /spl mu/m CMOS technology, and its power consumption is 6 mW with 3.3 V power supply. The device was fully characterized and achieves a dynamic range of 50 dB with a light power density of 150 nW/mm/sup 2/ and a frame rate of 30 frame/s. The measured fixed pattern noise corresponds to 1.1% of the saturation level. The sensor's dynamic range can be extended up to 96 dB using the double-sampling technique.

A CMOS image sensor with programmable pixel-level analog processing

A 128 times 64 pixel programmable vision sensor performs real-time analog image processing over high dynamic range images is reported. The pixel-parallel single instruction multiple data (SIMD) architecture executes real-time spatio-temporal filtering with 2.8 GOPS/mm2 and large flexibility in coefficient assignment. The sensor uses time-based and pulse-based operating modalities to execute spatio-temporal filtering on images with dynamic range up to about 100 dB. The in-pixel processing is based on two operations: the absolute value of voltage difference and accumulation of partial results. Feature extraction from the entire image is also possible without the need for image dispatching, thus optimizing both processing speed and video bandwidth. The 32.6 mum square pixel, with a fill-factor of 24%, consists of two analog memories and 28 transistors. The sensor, fabricated in 0.35 mum CMOS technology, gives a fixed pattern noise (FPN) of 0.8% and power consumption of 14 mW at 3.3 V.

A 100 dB Dynamic-Range CMOS Vision Sensor With Programmable Image Processing and Global Feature Extraction

This paper presents a smart sensor for an eye tracker using pixel-level analog image processing to eliminate the needs of many peripherals and the high power consumption of the conventional eye trackers. The pixel-level image processing was implemented with floating gate capacitors and nonlinear circuit computations. The prototype chip was fabricated for an 80 times 60 smart CMOS image sensor (CIS) pixel array whose pixel pitch is 22.4 times 22.4 mum2 in a 0.35-mum CMOS process. The test results show plusmnradic(2) pixel error and 200-mus processing time. The power consumption is 100 mW with a 3.3 V supply voltage and the silicon area is 7.5 mm2.

A 200 $\mu$ s Processing Time Smart Image Sensor for an Eye Tracker Using Pixel-Level Analog Image Processing

We present a single-chip integration of a CMOS image sensor with an embedded flexible processing array and dedicated analog-to-digital converter. The processor array is designed to perform convolution and transformation algorithms with arbitrary kernels. It has been designed to carry out the multiplication of analog image data with given digital kernel coefficients and to add up the results. The processor array is an analog implementation of a highly parallel architecture which is scalable to any desired sensor resolution while preserving video-rate operation. A prototype implementation has been realized in a 0.6-/spl mu/m CMOS technology. Switched current technique has been applied to obtain compact and robust circuits. The prototype's sensor resolution is 64 /spl times/ 128 pixels. The processor array occupies a small chip area and consumes only a small percentage of the power (250 /spl mu/W) of the whole image sensor.

CMOS image sensor with mixed-signal processor array

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CMOS image sensor with mixed-signal processor array