A systematic methodology for layout optimization of active devices for millimeter-wave (mm-wave) application is proposed. A hybrid mm-wave modeling technique was developed to extend the validity of the device compact models up to 100 GHz. These methods resulted in the design of a customized 90 nm device layout which yields an extrapolated of 300 GHz from an intrinsic device . The device is incorporated into a low-power 60 GHz amplifier consuming 10.5 mW, providing 12.2 dB of gain, and an output of 4 dBm. An experimental three-stage 104 GHz tuned amplifier has a measured peak gain of 9.3 dB. Finally, a Colpitts oscillator operating at 104 GHz delivers up to 5 dBm of output power while consuming 6.5 mW.

Millimeter-Wave Devices and Circuit Blocks up to 104 GHz in 90 nm CMOS

In this paper, we provide an extensive experimental and theoretical study of the benefits of patterned ground shield interconnect transmission lines over more conventional layouts in advanced integrated-circuit processes. As part of this experimental work, we present the first comparative study taken on truly differential transmission line test structures. Our experimental results obtained on transmission lines with patterned ground shields are compared against a predictive compact equivalent-circuit model. This model employs exact closed-form expressions for the inductances, and describes key performance figures such as characteristic impedance and attenuation loss with excellent accuracy

Low-Loss Patterned Ground Shield Interconnect Transmission Lines in Advanced IC Processes

Corrections on "Low-Loss Patterned Ground Shield Interconnect Transmission Lines in Advanced IC Processes"

We report record RF FET performance in 65 and 90-nm silicon-on-insulator (SOI) CMOS technologies featuring measured gate lengths from 27 to 43 nm and analyze factors contributing to that performance The effect of layout and geometry optimization as well as channel length scaling is investigated to improve RF performance, namely fT, and fMAX A peak fT of 330 GHz is measured in a fully-wired 65-nm NFET A complete de-embedding method to accurately determine RF characteristics of the intrinsic 90-nm SOI NFET results in a peak fT of 290 GHz and an fMAX of 450 GHz

Record RF performance of sub-46 nm L/sub gate/ NFETs in microprocessor SOI CMOS technologies

This work details the harmful effect of parasitic resistances and capacitances on RF figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) FD SOI n-MOSFETs. It is demonstrated that intrinsically, UTBB device can reach very high cut-off frequency (fT) provided the reduction of parasitic elements. In addition, based on device simulation, we demonstrate that with appropriate configuration, Asymmetric Double Gate (ADG) regime provides a slight improvement of RF figures-of-merit.

Effect of parasitic elements on UTBB FD SOI MOSFETs RF figures of merit

We have optimized 3 key RF devices realized in standard logic 90 nm CMOS technology and report a record performance in terms of n-MOS maximum oscillation frequency f/sub max/ (280 GHz), varactor tuning range and varactor and inductor quality factor.

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Record RF performance of standard 90 nm CMOS technology

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Record RF performance of standard 90 nm CMOS technology