A novel cooling device fully built in silicon technology is presented. The new concept developed in this work consists of micromachining the bottom side of the circuit wafer in order to embed heat sinking microchannels directly into the silicon material. These microchannels are then sealed, by a direct wafer bonding procedure, with another silicon wafer where microchannels and inlet-outlet nozzles are micromachined too. A cooling fluid (water) is then forced through the array of channel to convey heat outside the chip. Such a configuration presents advantages to provide a significant reduction of the cooler overall dimensions, to reduce the number of the involved materials and to be compatible with integrated circuit fabrication procedures, In this study analytical tools were used in order to get a global evaluation of all the thermal resistances characteristic of such devices. Using these adequate analytic models with appropriate approximations, a global optimization procedure was then applied and led to the definition of he optimum dimensions of the silicon micro heat sink. The realization procedure was then carried out in a clean room environment. First experimental characterization results obtained from the earlier prototypes demonstrated that the thermal properties of this silicon-based cooling device are satisfactory and can be reasonably compared to those of commercially available copper micro heat sinking components.

Analytic modeling, optimization, and realization of cooling devices in silicon technology

A method is described for fabricating a module having a chip attached to a carrier substrate, wherein a guide substrate transparent to ablation radiation is used. A removable layer is provided on a surface of the guide substrate. A first alignment guide is formed on the removable layer, and a second alignment guide is formed on a front surface of the chip. The chip is aligned to the guide substrate by contacting the second alignment guide to the first alignment guide; the chip is then attached to the guide substrate. The carrier substrate is attached to the chip at the back surface of the chip. The interface between the removable layer and the guide substrate is then ablated using radiation (typically laser radiation) transmitted through the guide substrate, thereby detaching the guide substrate. Thin films with metal interconnections may then be provided on the front surface of the chip.

Process for precision alignment of chips for mounting on a substrate

A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. The stud and via are aligned and connected, thereby permitting fine-pitch chip placement and electrical interconnections. A chip support is then attached to the device. A temporary chip alignment structure includes a transparent plate exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density. The device may include passive components located on separate chips, so that the device includes chips with and without active devices.

Process for making fine pitch connections between devices and structure made by the process

A method of low-temperature (150-300° C.) patterned wafer bonding of complex 3D MEMS comprising providing a first pre-processed wafer having a first surface and a second pre-processed wafer having a second surface. Photosensitive benzocyclobutene (BCB) polymer is then applied to the first surface of the first wafer in a predetermined pattern to define a bonding layer. The second wafer is then bonded to the first wafer only along the bonding layer.

Low-temperature patterned wafer bonding with photosensitive benzocyclobutene (BCB) and 3D MEMS (microelectromechanical systems) structure fabrication

Chronically implantable, wireless neural interfaces require biocompatible, long term stable, and high density integration of all functional sub-components. For this, the integration and interconnection concept of the wireless neural interface was proposed and interconnection materials and methods were investigated and characterized. The module consists of an electronics IC assembled to an electrode array. Thin film flex coils are glued onto the back side of the IC. The IC was interconnected by AuSn reflow flip chip bonding on the backside of the Utah electrode array (UEA) and off-chip electric components were SnCu0.7 soldered on the integrated IC/UEA module to guarantee a reliable connectivity.

Biocompatible hybrid flip chip microsystem integration for next generation wireless neural interfaces

With the current trend to ever faster clock rates the propagation delays between the chips constitute a significant portion of the clock cycle. Mounting both active and passive devices as closely together as possible will therefore boost system's performance. Although flip-chipped devices have good performance, design constraints may prevent the placement of pads to comply with flip chip design rules. An additional advantage of the embedding technology is the possibility to employ 3-D stacking, the highest package density. Bare dice and standard passive components were embedded into a ceramic substrate to achieve a common, planar surface. Hence by employing thin-film processing all components can be directly interconnected to the copper routing of the module. Benzocylobutene (BCB) with its low curing temperature is preferred as dielectrical polymer for the embedding technology. Application of bonding or soldering techniques which might limit the reliability is avoided. This offers excellent electrical properties of the wiring system. By planarizing the reverse side of the MCM a low thermal resistance between heat sink and dice can be accomplished simultaneously for all embedded components. An SRAM MCM and a Thermotest MCM demonstrate the facibility of the embedding technology.

Embedding technology-a chip-first approach using BCB

MCM-D with Embedded Active and Passive Components

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Embedding technology-a chip-first approach using BCB

MCM-D with Embedded Active and Passive Components